A.6 System Control Block Description
The System Control Block (SCB) contains vectors for servicing interrupts and
exceptions. The SCB address should be aligned on a page boundary. The
SCB address is contained in the System Control Block Base register (SCBB)
(Figure A–5). Microcode forces a longword-aligned SCBB by clearing bits [01:00]
of the new value before loading the register.
Figure A–5 System Control Block Base Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
07
06
05
04
03
02
01
00
15
14
13
12
11
10
09
08
Physical Page Address of SCB
SBZ
0
Physical Page Address of SCB
0
MR−0021−93RAGS
An SCB vector is an aligned longword in the SCB through which the CPU
microcode dispatches interrupts and exceptions. Each SCB vector has the format
shown in Figure A–6.
Figure A–6 System Control Block Vector Format
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
07
06
05
04
03
02
01
00
15
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11
10
09
08
Longword Address of Service Routine
Code
MR−0022−93RAGS
Longword Address of Service Routine
[31:02]: Longword Address - Virtual address of the service routine for the
interrupt or exception. The routine must be longword aligned since the microcode
forces the two low-order bits to 0.
[01:00]: Code - The code field is defined in Table A–5.
Table A–5 Code Field Definition
Code
Definition
00
The event is to be serviced on the kernel stack unless the CPU is already on the
interrupt stack, in which case the event is serviced on the interrupt stack.
(continued on next page)
A–10 Miscellaneous System Information