Table A–4 (Cont.) Xlink Mode Coding
Code
Mode
101
Resync Slave
110
Resync Master
111
Not Used
[27:26]: - Not used.
[25]: LCK - Lock. Latched when an error occurs during an interlock I/O access.
(Interlock access refers to the special I/O access mode.)
[24]: RSA - Resync Abort. Latched when an error occurs during resync mode.
Resync mode is automatically canceled.
[23]: CBG - Cable Gone. Latched when a cable gone signal is detected. CBG set
will force the Xlink to the off mode.
[22]: PWG - Power Gone. Set when the other zone power gone signal is detected.
PWG set will force the Xlink to the off mode.
[21]: CPB - Clock Phase Error (Zone B). Latches a high level assertion on the
Clock Phase Error line coming from the Xlink. The high level will remain until a
1 is written to the bit. If the Clock Phase Error signal line is still high after the
write 1 to clear, the bit is again set to 1.
[20]: CPA - Clock Phase Error (Zone A). Latches a high level assertion on the
Clock Phase Error line coming from the Xlink. The high level will remain until a
1 is written to the bit. If the Clock Phase Error signal line is still high after the
write 1 to clear, the bit is again set to 1.
[19]: HTB - Halt Error (Zone B). Latches a high level assertion on the Halt
Request line coming from the Xlink. The high level will remain until a 1 is
written to the bit. If the Halt Error signal line is still high after the write 1 to
clear, the bit is again set to 1.
[18]: HTA - Halt Error (Zone A). Latches a high level assertion on the Halt
Request line coming from the Xlink. The high level will remain until a 1 is
written to the bit. If the Halt Error signal line is still high after the write 1 to
clear, the bit is again set to a 1.
[17]: MFB - CPMF (Zone B). Set when the error logic determines that a CPMF
is required.
[16]: MFA - CPMF (Zone A). Set when the error logic determines that a CPMF
is required.
[15]: MDB - Memory Double-Bit Error (Zone B). Set when a double-bit ECC
error or single-bit ECC error is detected during memory writes on the internal
Jet Bus ECC checker. This causes a CPMF.
[14]: MDA - Memory Double-Bit Error (Zone A). Set when a double-bit ECC error
or single-bit ECC error is detected during memory writes on the internal Jet Bus
ECC checker. This causes a CPMF.
[13]: MSB - Memory Single-Bit Error (Zone B). Set when a single-bit ECC error
is detected in memory during a read and the JXD was not the requester of the
data. The bit is set regardless of the state of the Error Enable bit. The error
is automatically corrected at the CPU. An IPL26 interrupt is generated causing
Miscellaneous System Information A–5