Table 4–37 (Cont.) DCB Entry Components
Component
Length
Description
Ethernet
address
32 bytes
Module Ethernet address. Follows the DEC STD format.
Valid only for CPU module and LANCE adapter card.
Copied from the Ethernet EEPROM by firmware for the
CPU. Copied from the LANCE ROM for the LANCE adapter
card.
Extended data
32 bytes
Module-specific data. The field is copied by firmware from
the functional firmware ROM.
Memory size
4 bytes
Size of the module’s memory in 512 byte segments.
For CPU refers to the size of main memory.
For I/O ATM refers to the size of local (SOC) memory.
For interface modules refers to the size of buffer RAM.
SubDCB
4 bytes
Offset to the module SubDCB (Sub-Device Configuration
Block). Offset is the byte offset (signed) from the base of the
DCB. Is 0 if no SubDCB available.
Reserved
64 bytes
Reserved for future use.
4.8.2.1 Sub-Device Configuration Blocks
The SubDCBs reflect the configuration of the interface or memory modules
attached to a module. SubDCBs may be available for the CPU and I/O ATM
modules. The SubDCB is built by firmware during the power up sequence and
updated each time INIT and BOOT are executed.
A SubDCB is present when there are interface modules attached to a given
module and its existence is represented in that module’s DCB entry. When the
SubDCB offset field on a DCB entry is nonzero, the value is used to calculate the
location of its SubDCB block. If the SubDCB offset field on a DCB entry is zero,
there is no SubDCB block present (that is, no interface modules are attached to
that module).
The format of a SubDCB is the same as for the DCB block. The field containing
the number of entries follows the same format as a DCB entry (except the CPU
module SubDCB). Figure 4–15 shows how the SubDCBs are linked to the DCB.
Error Handling and Analysis 4–63