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PPC2+™ Operation and Maintenance Manual
Page 119
©2001 DH Instruments, Inc.
4.5.3 STANDARD EVENT REGISTER
The PPC2+ contains an 8 bit Standard event register that reflects specific PPC2+ events.
Enabled events in this register will set or clear the ESB bit of the Status Byte Register.
Table 15. 8 Bit Standard Event Register
PON
(128)
URQ
(64)
CMD
(32)
EXE
(16)
DDE
(8)
QYE
(4)
RQC
(2)
OPC
(1)
This register can be read using the “*ESR?” query, Each of these status bits can set the ESB
bit of the Status Byte Register, causing a SRQ to occur IF the ESB bit is enabled to do so.
The Standard Event Status Enable Register (“
∗
ESE” program message ) determines which of
these flags are able to assert the ESB bit. The description of these bits are given as:
•
PON: Power On (Bit 7)
Indicates that the PPC2+ power has been cycled since the last time this bit was read
or cleared.
•
URQ: User Request (Bit 6)
Indicates that the PPC2+ was set to local operation manually from the front panel by the
user (pressing the [ESC] key).
•
Command Error (Bit 5)
Indicates that a remote command error has occurred. A command error is typically a
syntax error in the use of a correct program message.
•
EXE: Execution Error (Bit 4)
Indicates if a remote program message cannot be processed due to device
related condition.
•
DDE: Device Dependent Error (Bit 3)
Indicates that an internal error has occurred in the PPC2+ such as a transducer time-out.
•
QYE: Query Error (Bit 2)
Indicates that an error has occurred in the protocol for program message communications.
This is typically caused by a program message being sent to the PPC2+ without reading a
waiting reply.
•
RQC: Request Control (Bit 1)
This bit is not supported as the PPC2+ cannot become the active controller in charge.
•
OPC: Operation Complete (Bit 0)
Indicates that the PPC2+ has completed all requested functions.