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Spyder3 GigE Vision SG-14 Monochrome Cameras User’s Manual
03-032-20123-01
Teledyne DALSA
N ote that all external inp u ts (from the cam era, TTL inp u ts, and PLC controls) are resynchronized . The
ou tp u ts from the look-u p table are synchronou s.
The LUT is p rogram m ed u sing a sim p le langu age. This langu age allow s you to create logical equ ations
that sp ecify the cond itions that set p articu lar ou tp u ts
N ote: There is a d elay of tw o clock cycles betw een the inp u ts of the LUT and its ou tp u ts. A clock cycle has
a p eriod of 30 nanosecond s, so the d elay is 60 nanosecond s.
The signals in the PLC Control Block are d efined in the tables below .
Inp u ts to Cam Exp ert are labeled I
n
(w here n is an integer from 0 to 7) and ou tp u ts are labeled Q
n
(w here
n is an integer from 0 to 15).
PLC Input Signal Routing Block
The follow ing cod e sets the first entry in the PLC’s signal rou ting block: Setting the Signal Rou ting Block
is com p licated by the fact that each entry in the table has a d ifferent set of enu m erated inp u ts. So for
exam p le, a valu e of 0 for
i0
(i.e. GPIO Inp u t 0) m eans som ething d ifferent for
i6
(i.e. Pu lse Generator 1
Ou tp u t). Below is a table of enu m erated valu es w ith resp ect to each entry.
For m ore inform ation on the Signal Rou ting Block, refer to the section below , Signal Rou ting Block on
p age 89.