Document Number: 002-10635 Rev. *I
Page
235 of 325
S6J3310/20/30/40 Series
(2) DDR-HSSPI Interface Timing (DDR Mode)
(T
A
: Recommended operating conditions, Vcc3 = 3.3 V ± 0.3 V, V
SS
= DV
SS
= AV
SS
= 0.0 V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit Remarks
Min
Max
HSSPI clock cycle
t
cyc
M_SCLK0
(CL = 20 pF,
I
OL
= -10 mA,
I
OH
= 10 mA),
12.5
-
ns
M_SCLK↑ ->
delayed sample
clock↑
t
spcnt
0
31.5
ns
M_SDATA ->
M_SLCK↑
Input setup time
t
isdata
M_SDATA0_0-3
M_SDATA1_0-3
*1
-
ns
M_SLCK↑ ->
M_SDATA
Input hold time
t
ihdata
M_SDATA0_0-3
M_SDATA1_0-3
*1
-
ns
M_SCLK↑ ->
M_SDATA
Output delay time
t
oddata
M_SDATA0_0-3
M_SDATA1_0-3
-
tcyc/4 +
1.5
ns
M_SCLK↑ ->
M_SDATA
Output hold time
t
ohdata
M_SDATA0_0-3
M_SDATA1_0-3
Tcyc/4 - 1.0
-
ns
M_SCLK↑ ->
M_SSEL
Output delay time
t
odsel
M_SSEL0, 1
-
15.75+(SS2C
D+0.5)*tcyc
-
ns
M_SCLK↑ ->
M_SSEL
Output hold time
t
ohsel
M_SSEL0, 1
0.75*tcyc -
2.0
-
ns
Notes: This is Target Spec.
t
cyc
V
IH
V
IL
G_SCLK0
G_SDATA0_0-3,
G_SDATA1_0-3
(input timing)
V
OH
V
OH
V
IH
V
IL
valid
t
isdata
delayed
sample clock
t
ihdata
V
OH
t
spcnt
V
OH
V
OL
G_SDATA0_0-3,
G_SDATA1_0-3
(output timing)
V
OH
V
OL
valid
t
oddata
t
ohdata
V
OH
V
OL
GSSEL0, 1
(output timing)
V
OH
V
OL
valid
t
odsel
t
ohsel
M_SDATA0_0-3,
M_SDATA1_0-3
M_SDATA0_0-3,
M_SDATA1_0-3
M_SCLK0
M_SSEL0,1