Document Number: 002-10635 Rev. *I
Page
236 of 325
S6J3310/20/30/40 Series
−
SS2CD [1:0] should be configured as 01, 10, or 11.
−
For *1, the delay of the delay sample clock can be configured (DLP function)
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
t
cyc
V
IH
V
IL
G_SCLK0
G_SDATA0_0-3,
G_SDATA1_0-3
(input timing)
V
OH
V
OH
V
IH
V
IL
valid
t
isdata
delayed
sample clock
t
ihdata
V
OH
t
spcnt
G_SDATA0_0-3,
G_SDATA1_0-3
(output timing)
valid
t
oddata
GSSEL0, 1
(output timing)
valid
t
odsel
t
ohsel
valid
V
OL
t
ohdata
t
oddata
t
ohdata
M_SDATA0_0-3,
M_SDATA1_0-3
M_SDATA0_0-3,
M_SDATA1_0-3
M_SCLK0
M_SSEL0,1