Document Number: 002-10635 Rev. *I
Page
11 of 325
S6J3310/20/30/40 Series
Feature
Description
Embedded
Program/Work Flash
Memory
Embedded Program Flash can be accessed with 0-wait-cycle if CPU frequency is 80MHz or less.
0-wait-cycle: 80MHz or less.
1-wait-cycle: 160MHz or less.
2-wait-cycle: more than 160MHz.
Work Flash can be accessed with 0-wait-cycle if CPU frequency is 12.5MHz or less.
6-wait-cycle: 80MHz or less.
12-wait-cycle: 160MHz or less.
The wait-cycle setting see the
Traveo
TM
Platform Hardware Manual
in details.
The CLK_FCLK maximum frequency should be referred in
Erase suspend is supported. Reading and writing to the other sector are possible when Flash
Erase is suspended.
Serial Flash programing and Parallel Flash programing are supported.
Margin mode is not supported.
Internal Power Domain
PD1: Always ON
PD2: Cortex R5F platform/ GDC/ additional peripherals
PD4: Backup RAM in Always On domain
PD6: Peripherals in Always On domain
* The chapter of the block diagram explains in detail.
Power Supply
5 V, and 3 V, 1.2 V external power supply is required.
Built in LDO provides internal power supply for Always On region (PD1).
1.2 V external power supply control pin is supported.
3 V external power supply could be controlled by GPIO.
There are constraints of power on/off sequence.
Low Voltage Detection
LVD for external voltage is supported.
LVD for internal voltage is supported.
See
and
Low voltage detection for
RAM retention (RVD)
RVD for RAM retention is effective during the standby mode only. That is, it is only for the
Backup RAM of 32KB that the function is available.
Resource inter-connect
The output signal of some resources can be inputted to the other resource.
I/O Ports
5 V general purpose I/O
3 V general purpose I/O
Multi input level and multi output drivability
Pull-up, pull-down function is available.
Resource input and output is multiplexed.
+B input is allowed many pins of 3.3 V, 5 V and 3.3 V/5 V I/O domain.
A/D Converter
12 bit resolution, 2 unit (Unit0 is possible to select channels 4-31. Unit1 is possible to select
channels 32-63.)
48 channels of analog input for TEQFP208
48 channels of analog input for TEQFP176
35 channel of analog input for TEQFP144
24 channels of them are shared with the SMC for TEQFP208/176/144
External trigger and timer trigger are available.
The description of the A/D converter function should be referred in the
S6J3300 Hardware
Manual
. Though the chapter of I/O port in
Traveo
TM
Platform Hardware Manual
describes
another A/D converter function, do not refer it.
A/D Channel Control Register (ADC12Bn_CHCTRL0) [bit5:0] ANIN[5:0]: Analog Input Selection
bits.
This register setting is possible of channel 0-31 (the register value is 00_0000 to 01_1111).
AN39 to AN63 are not support for S6J33xxxAx, S6J33xxxCx, S6J33xxxEx, and S6J33xxxGx
option.
CRC
See the
Traveo
TM
Platform Hardware Manual
in detail.