Document Number: 002-10635 Rev. *I
Page
275 of 325
S6J3310/20/30/40 Series
Page
Section
Change Results
225
9.Electric
Characteristics
9.1.4.16 DDR-
HSSPI
Revised as below:
Error)
(16-2) DDR-HSSPI Interface Timing (DDR mode)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Max
HSSPI clock cycle
t
cyc
M_SCLK0
(CL = 20pF,
I
OL
=-10mA,
I
OH
=10mA),
10
-
ns
M_SCLK↑ ->
delayed sample clock↑
t
spcnt
0
tcyc
ns
M_SDATA -> delayed
sample clock↑
Input setup time
t
isdata
M_SDATA0_0-3
M_SDATA1_0-3
1.0
-
ns
delayed sample clock↑
-> M_SDATA
Input hold time
t
ihdata
M_SDATA0_0-3
M_SDATA1_0-3
1.0
-
ns
M_SCLK↑ ->
M_SDATA
Output delay time
t
oddata
M_SDATA0_0-3
M_SDATA1_0-3
-
3.5
ns
t
cyc
/2-1.5ns
M_SCLK↑ ->
M_SDATA
Output hold time
t
ohdata
M_SDATA0_0-3
M_SDATA1_0-3
1.5
-
ns
M_SCLK↑ -> M_SSEL
Output delay time
t
odsel
M_SSEL0, 1
-
7.0
ns
t
cyc
-3.0ns
M_SCLK↑ -> M_SSEL
Output hold time
t
ohsel
M_SSEL0, 1
3.0
-
ns
Notes: This is Target Spec.
Correct)
(2)DDR-HSSPI Interface Timing (DDR mode)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remark
s
Min
Max
HSSPI clock cycle
t
cyc
M_SCLK0
(CL = 20pF,
I
OL
=-10mA,
I
OH
=10mA),
12.5
-
ns
M_SCLK↑ ->
delayed sample clock↑
t
spcnt
0
31.5
ns
M_SDATA ->
M_SLCK↑
Input setup time
t
isdata
M_SDATA0_0-3
M_SDATA1_0-3
*1
-
ns
M_SLCK↑ ->
M_SDATA
Input hold time
t
ihdata
M_SDATA0_0-3
M_SDATA1_0-3
*1
-
ns
M_SCLK↑ ->
M_SDATA
Output delay time
t
oddata
M_SDATA0_0-3
M_SDATA1_0-3
-
t
cyc
/4 + 1.5
ns
M_SCLK↑ ->
M_SDATA
Output hold time
t
ohdata
M_SDATA0_0-3
M_SDATA1_0-3
Tcyc/4 - 1.0
-
ns
M_SCLK↑ -> M_SSEL
Output delay time
t
odsel
M_SSEL0, 1
-15.75+
(SS2CD+0.5)*t
cyc
-
ns
M_SCLK↑ -> M_SSEL
Output hold time
t
ohsel
M_SSEL0, 1
0.75*t
cyc
- 2.0
-
ns
Notes: This is Target Spec.
−
SS2CD [1:0] should be configured as 01, 10, or 11.
−
For *1, the delay of the delay sample clock can be configured (DLP function)