Document Number: 002-10635 Rev. *I
Page
217 of 325
S6J3310/20/30/40 Series
I
2
C timing (SMR:MD2-0 = 0b100)
(T
A
: Recommended operating conditions, Vcc5 = Vcc53 = 5.0 V ± 10 %, V
CC
12 = 1.15 V ± 0.06 V, V
SS
= 0.0 V)
Parameter
Symbol
Pin Name
Conditions
Standard
Mode
Fast
Mode
Unit Remarks
Min
Max
Min
Max
SCL clock
frequency
f
SCL
SCL0, SCL1,
SCL4,
SCL8 to SCL12,
SCL16 to SCL17
C
L
= 50 pF,
R = (Vp/I
OL
)
*1
0
100
0
400
kHz
Repeat "start"
condition hold time
SDA↓ → SCL↓
t
HDSTA
SDA0, SDA1,
SDA4
SDA8 to SDA12,
SDA16 to SDA17,
SCL0, SCL1,
SCL4,
SCL8 to SCL12,
SCL16 to SCL17
4.0
-
0.6
-
µs
Period of "L" for
SCL clock
t
LOW
SCL0, SCL1,
SCL4,
SCL8 to SCL12,
SCL16 to SCL17
4.7
-
1.3
-
µs
Period of "H" for
SCL clock
t
HIGH
4.0
-
0.6
-
µs
Repeat "start"
condition setup
time
SCL↑ → SDA↓
t
SUSTA
SDA0, SDA1,
SDA4
SDA8 to SDA12,
SDA16 to SDA17,
SCL0, SCL1,
SCL4,
SCL8 to SCL12,
SCL16 to SCL17
4.7
-
0.6
-
µs
Data hold time
SCL↓ → SDA↓↑
t
HDDAT
0
3.45
*2
0
0.9
*3
µs
Data setup time
SDA↓↑ → SCL↑
t
SUDAT
250
-
100
-
ns
"Stop" condition
setup time
SCL↑ → SDA↑
t
SUSTO
4.0
-
0.6
-
µs
Bus-free time
between "stop"
condition and
"start"
condition
t
BUF
-
4.7
-
1.3
-
µs
Noise filter
t
SP
-
t
NFT
*4
-
t
NFT
*4
-
ns
Notes: Only ch.16 and ch.17 are standard mode/high-speed mode correspondence. In ch.0, ch.1, ch.4, and ch.8 to ch.12, only a
standard mode is correspondence.
*1: R and C
L
represent the pull-up resistance and load capacitance of the SCL and SDA output lines,
respectively.
Vp shows that the power-supply voltage of the pull-up resistor and I
OL
shows the V
OL
guarantee current.
*2: The maximum t
HDDAT
only has to be met if the device does not extend the "L" width (t
LOW
) of the SCL
signal.
*3: A fast mode I
2
C bus device can be used on a standard mode I
2
C bus system as long as the
device satisfies the requirement of "t
SUDAT
≥ 250 ns".
*4: t
NFT
= (NFCR:NFT[4:0]+1) x 2 x t
CLK_LCP0A
(ch.0, ch.1, ch4)
t
NFT
= (NFCR:NFT[4:0]+1) x 2 x t
CLK_LCP1A
(ch.8 to ch.12)
t
NFT
= (NFCR:NFT[4:0]+1) x 2 x t
CLK_COMP
(ch.16 to ch.17)