Document Number: 002-10635 Rev. *I
Page
196 of 325
S6J3310/20/30/40 Series
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Max
Serial clock
cycle time
t
SCYC
SCK2_0, SCK3_0
Master
Mode
(CL = 20 pF,
I
OL
= -10 mA,
I
OH
= 10 mA)
2t
CLK_LCPnA
*1
-
ns
SCK ↓ → SOT
delay time
t
SHOVI
SCK2_0, SCK3_0,
SOT2_0, SOT3_0
-7.5
+7.5
ns
Valid SIN → SCK
↑
setup time
t
IVSLI
SCK2_0, SCK3_0,
SIN2_0, SIN3_0
10
-
ns
SCK ↑→ Valid SIN
hold time
t
SLIXI
0
-
ns
Serial clock
"H" pulse width
t
SHSL
SCK0 to SCK4,
SCK8 to SCK12
Slave
Mode
(CL = 20 pF,
I
OL
= -5 mA,
I
OH
= 5 mA)
4t
CLK_LCPnA
*1
-
ns
SCK16 to SCK17
4t
CLK_COMP
-
ns
Serial clock
"L" pulse width
t
SLSH
SCK0 to SCK4,
SCK8 to SCK12
4t
CLK_LCPnA
*1
-
ns
SCK16 to SCK17
4t
CLK_COMP
-
ns
SCK ↑ → SOT
delay time
t
SHOVE
SCK0 to SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SOT0 to SOT4,
SOT8 to SOT12,
SOT16 to SOT17
-
40
ns
Valid SIN → SCK
↓
setup time
t
IVSLE
SCK0 to SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SIN0 to SIN4,
SIN8 to SIN12,
SIN16 to SIN17
10
-
ns
SCK ↓ → Valid
SIN
hold time
t
SLIXE
10
-
ns
SCK falling time
t
F
SCK0 to SCK4,
SCK8 to SCK12,
SCK16 to SCK17
-
5
ns
SCK rising time
t
R
SCK0 to SCK4,
SCK8 to SCK12,
SCK16 to SCK17
-
5
ns
*1: n = 0:ch.0 to ch.4, n = 1:ch.8 to ch.12
Notes:
−
This table provides the alternate current standard for CLK synchronous mode.
−
CL is the load capability value connected to the pin at the test time.
−
The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the Traveo™ Platform Hardware Manual.