Document Number: 002-10635 Rev. *I
Page
234 of 325
S6J3310/20/30/40 Series
9.1.4.16
DDR-HSSPI
(1) DDR-HSSPI Interface Timing (SDR Mode)
(T
A
: Recommended operating conditions, Vcc3 = 3.3 V ± 0.3 V, V
SS
= DV
SS
= AV
SS
= 0.0 V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Max
HSSPI clock cycle
t
cyc
M_SCLK0
(CL = 20 pF,
I
OL
= -10 mA,
I
OH
= 10 mA),
10
-
ns
20
-
when Quad
Page Program
M_SCLK↑ ->
delayed sample
clock↑
t
spcnt
-
0
31.5
ns
M_SDATA ->
M_SLCK↑
Input setup time
t
isdata
M_SDATA0_0-3
M_SDATA1_0-3
*1
-
ns
M_SLCK↑ ->
M_SDATA
Input hold time
t
ihdata
M_SDATA0_0-3
M_SDATA1_0-3
*1
-
ns
M_SCLK↑ ->
M_SDATA
Output delay time
t
oddata
M_SDATA0_0-3
M_SDATA1_0-3
-
t
cyc
/2 + 2
ns
M_SCLK↑ ->
M_SDATA
Output hold time
t
ohdata
M_SDATA0_0-3
M_SDATA1_0-3
t
cyc
/2 - 3
-
ns
M_SCLK↑ -> M_SSEL
Output delay time
t
odsel
M_SSEL0, 1
-
12.00+(SS
2CD+0.5)*
t
cyc
-
ns
M_SCLK↑ -> M_SSEL
Output hold time
t
ohsel
M_SSEL0, 1
t
cyc
- 2
-
ns
Notes: This is Target Spec.
−
SS2CD [1:0] should be configured as 01, 10, or 11.
−
For *1, the delay of the delay sample clock can be configured (DLP function).