Cypress S6J331EJSESE20000, Руководство пользователя

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Document Number: 002-10635 Rev. *I Page
230 of 325
S6J3310/20/30/40 Series
9.1.4.15
External Bus Interface Timing
Clock Output Timing
(T
A
: Recommended operating conditions, Vcc53 = 5.0 V ± 10 %, V
SS
= 0.0 V)
(External load capacitance 16 pF)
Parameter Symbol Pin Name Conditions
Value
Unit Remarks
Min Max
Cycle time t
CYC
MCLK 2 mA is
selected in
ODR bit in
PPC_PCFGR
register.
62.5 - ns
Clock high width *1 t
CHCL
MCLK d
H
t
cyc
- 7 d
H
t
cyc
+ 7 ns
Clock low width *2 t
CLCH
MCLK d
L
t
cyc
- 7 d
L
t
cyc
+ 7 ns
*1: If division-ratio is even value, dH is equivalent to 0.5.
Otherwise, dH is calculated as the following.
dH = The number rounding "division-ratio x 0.5" down to the nearest integer / division-ratio
division-ratio is multiplication value among SYSDIV bit, HPMDIV bit and EXTBUSDIV bit setting.
ex). Setting SYSDIV to 1-division, HPMDIV to 7-division, EXTBUSDIV to 1-division, dH is calculated as 0.429.
*2: If division-ratio is even value, dL is equivalent to 0.5.
Otherwise, dL is calculated as the following.
dL = The number rounding "division-ratio x 0.5" up to the nearest integer / division-ratio
division-ratio is multiplication value among SYSDIV bit, HPMDIV bit and EXTBUSDIV bit setting.
ex). Setting SYSDIV to 1-division, HPMDIV to 7-division, EXTBUSDIV to 1-division, dL is calculated as 0.571.
−
Clock output timing