Document Number: 002-10635 Rev. *I
Page
229 of 325
S6J3310/20/30/40 Series
9.1.4.14
Display Controller
(1) Display Controller0 Timing (TTL Mode)
(T
A
: Recommended operating conditions, Vcc53 = 5.0 V ± 10 %, 3.3 V ± 0.3 V, V
SS
= DV
SS
= AV
SS
= 0.0 V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Max
Clock Cycle
t
DC0CYC
DSP0_CLK
(CL = 20 pF,
I
OL
= -15 mA,
I
OH
= 15 mA),
25
-
ns
Output delay from
DSP0_CLK↑
|t
DC0D
|
DSP0_R7-0
DSP0_G7-0
DSP0_B7-0
DSP0_EN
DSP0_HSYNC
DSP0_VSYNC
(CL = 20 pF,
I
OL
= -5 mA,
I
OH
= 5 mA)
-
3.2
ns
Output data valid
time
t
DC0V
DSP0_R7-0
DSP0_G7-0
DSP0_B7-0
DSP0_EN
DSP0_HSYNC
DSP0_VSYNC
21.8
-
ns
t
DC0CYC
- 3.3
ns+0.1 ns
Notes: This is Target Spec.
DSP0_CLK
V
OH
V
OH
DSP0_DATA0_11-0
DSP0_DATA1_11-0
DSP0_CTRL11-0
valid
t
DC0D
t
DC0V