Cypress enCoRe V CY7C643 Series, Техническое справочное руководство

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enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 93
System Resources Register Summary
The following table lists all the enCoRe V registers for the system resources, in address order, within their system resource
configuration. The bits that are grayed out are reserved bits. If you write these bits, always write them with a value of ‘0’.
Summary Table of the System Resource Registers
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
DIGITAL CLOCK REGISTERS (page 99 )
1,BDh USB_MISC_CR
USB_SE_
EN
USB_ON
USB_CLK_
ON
RW : 0
1,DDh OUT_P1 P16D P16EN P10EN RW : 00
1,E0h OSC_CR0 X32ON Disable Buzz No Buzz Sleep[1:0] CPU Speed[2:0] RW : 01
1,E2h OSC_CR2 CLK48MEN
EXT-
CLKEN
RSVD RW : 0
I2C SLAVE REGISTERS (page 106 )
0,C8h I2C_XCFG HW Addr En RW : 0
0,CAh I2C_ADDR Slave Address[6:0] RW : 00
0,D6h I2C_CFG PSelect Stop IE Clock Rate[1:0] Enable RW : 00
0,D7h I2C_SCR Bus Error
Stop
Status
ACK Address Transmit LRB
Byte
Complete
# : 00
0,D8h I2C_DR Data[7:0] RW : 00
SYSTEM RESET REGISTERS (page 116 )
x,FEh CPU_SCR1 IRESS SLIMO[1:0] IRAMDIS # : 0
x,FFh CPU_SCR0 GIES WDRS PORS Sleep STOP # : XX
POR REGISTERS (page 121 )
1,E3h VLT_CR HPOR PORLEV[1:0] LVDTBEN VM[2:0] RW : 00
1,E4h VLT_CMP NoWrite POR_EXT LVD R : #
SPI REGISTERS (page 125 )
0,29h SPI_TXR Data[7:0] W : 00
0,2Ah SPI_RXR Data[7:0] R : 00
0,2Bh SPI_CR LSb First Overrun
SPI
Complete
TX Reg
Empty
RX Reg Full
Clock
Phase
Clock
Polarity
Enable # : 00
1,29h SPI_CFG Clock Sel [2:0] Bypass SS_ SS_EN_ Int Sel Slave RW : 00
PROGRAMMABLE TIMER REGISTERS (page 139 )
0,B0h PT0_CFG CLKSEL One Shot START RW : 0
0,B1h PT0_DATA1 DATA[7:0] RW : 00
0,B2h PT0_DATA0 DATA[7:0] RW : 00
0,B3h PT1_CFG CLKSEL One Shot START RW : 0
0,B4h PT1_DATA1 DATA[7:0] RW : 00
0,B5h PT1_DATA0 DATA[7:0] RW : 00
0,B6h PT2_CFG CLKSEL One Shot START RW : 0
0,B7h PT2_DATA1 DATA[7:0] RW : 00
0,B8h PT2_DATA0 DATA[7:0] RW : 00
USB REGISTERS (page 147 )
0,58h PMAx_DR Data Byte[7:0] RW : 00
0,59h PMAx_DR Data Byte[7:0] RW : 00
0,5Ah PMAx_DR Data Byte[7:0] RW : 00
0,5Bh PMAx_DR Data Byte[7:0] RW : 00
0,5Ch PMAx_DR Data Byte[7:0] RW : 00
0,5Dh PMAx_DR Data Byte[7:0] RW : 00
0,5Eh PMAx_DR Data Byte[7:0] RW : 00
0,5Fh PMAx_DR Data Byte[7:0] RW : 00