Cypress enCoRe V CY7C643 Series, Техническое справочное руководство

Страница: 16 / 257

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 16
Pin Information
1.1.2
CY7C60445 enCoRe V LV 32-Pin Part Pinout
Table 1-2. 32-Pin QFN Part Pinout
2
Pin
No.
Digit
a
l
An
al
og
Name Description
CY7C60445 enCoRe V LV Devices
1 IOH I P0[1] Integrating input
2 IO I P2[7]
3 IO I P2[5] XTAL Out
4 IO I P2[3] XTAL In
5 IO I P2[1]
6 IO I P3[3]
7 IO I P3[1]
8 IOHR I P1[7] I2C SCL, SPI SS
9 IOHR I P1[5] I2C SDA, SPI MISO
10 IOHR I P1[3] SPI CLK
11 IOHR I P1[1]
TC CLK
1
, I2C SCL, SPI MOSI
12 Power Vss Ground pin
13 IOHR I P1[0]
TC DATA
1
, I2C SDA, SPI CLK
14 IOHR I P1[2]
15 IOHR I P1[4] EXTCLK
16 IOHR I P1[6]
17 Input XRES Active high external reset with internal pull down
18 IO I P3[0]
19 IO I P3[2]
20 IO I P2[0]
21 IO I P2[2]
22 IO I P2[4]
23 IO I P2[6]
24 IOH I P0[0]
25 IOH I P0[2]
26 IOH I P0[4]
27 IOH I P0[6]
28 Power Vdd Power pin
29 IOH I P0[7]
30 IOH I P0[5]
31 IOH I P0[3]
32 Power Vss Ground pin
Legend
A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.
1
These are the ISSP pins, which are not High-Z at POR.
2
The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not con-
nected to ground, it must be electrically floated and not connected to any other signal.
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P3[3]
QFN
(Top View)
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32
31
30
29
28 27 26
25
Vs
s
P0
[3
]
P0
[7
]
Vd
d
P0
[6
]
P0
[4
]
P0
[2
]
P3[1]
P1[7]
P0[0]
P2[6]
P3[0]
XRES
P1
[5
]
P1
[3
]
P1
[1
]
Vs
s
P1
[0
]
P1
[2
]
P1
[4
]
P1
[6
]
P2[4]
P2[2]
P2[0]
P3[2]
P0
[5
]