Cypress enCoRe V CY7C643 Series, Техническое справочное руководство

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enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 24
Core Register Summary
This table lists all the enCoRe V registers for the CPU core in
address
order within their system resource configuration. The
grayed out bits are reserved bits. If you write these bits, always write them with a value of ‘0’. For the core registers, the first
‘x’ in some
register
addresses represents either bank 0 or bank 1. These registers are listed throughout this manual in bank
0, even though they are also available in bank 1.
Summary Table of the Core Registers
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
M8C REGISTER (page 26 )
x,F7h CPU_F PgMode[1:0] XIO_1 XIO Carry Zero GIE RL : 02
RAM PAGING (SRAM) REGISTERS (page 38 )
x,6Ch TMP_DR0 Data[7:0] RW : 00
x,6Dh TMP_DR1 Data[7:0] RW : 00
x,6Eh TMP_DR2 Data[7:0] RW : 00
x,6Fh TMP_DR3 Data[7:0] RW : 00
0,D0h CUR_PP Page Bits[2:0] RW : 0
0,D1h STK_PP Page Bits[2:0] RW : 0
0,D3h IDX_PP Page Bits[2:0] RW : 0
0,D4h MVR_PP Page Bits[2:0] RW : 0
0,D5h MVW_PP Page Bits[2:0] RW : 0
INTERRUPT CONTROLLER REGISTERS (page 44 )
0,DAh INT_CLR0 I2C Sleep SPI GPIO Timer0 Reserved Reserved V Monitor RW : 00
0,DBh INT_CLR1 Endpoint3 Endpoint2 Endpoint1 Endpoint0 USB SOF USB Bus Rst Timer2 Timer1 RW : 00
0,DCh INT_CLR2 USB_WAKE Endpoint8 Endpoint7 Endpoint6 Endpoint5 Endpoint4 RW : 00
0,DEh INT_MSK2
USB
Wakeup
Endpoint8 Endpoint7 Endpoint6 Endpoint5 Endpoint4 RW : 00
0,DFh INT_MSK1 Endpoint3 Endpoint2 Endpoint1 Endpoint0 USB SOF
USB Bus
Reset
Timer2 Timer1 RW : 00
0,E0h INT_MSK0 I2C Sleep SPI GPIO Timer0 Reserved Reserved V Monitor RW : 00
0,E1h INT_SW_EN ENSWINT RW : 0
0,E2h INT_VC Pending Interrupt[7:0] RC : 00
GENERAL-PURPOSE I/O (GPIO) REGISTERS (page 56 )
0,00h PRT0DR Data[7:0] RW : 00
0,01h PRT0IE Interrupt Enables[7:0] RW : 00
0,04h PRT1DR Data[7:0] RW : 00
0,05h PRT1IE Interrupt Enables[7:0] RW : 00
0,08h PRT2DR Data[7:0] RW : 00
0,09h PRT2IE Interrupt Enables[7:0] RW : 00
0,0Ch PRT3DR Data[7:0] RW : 00
0,0Dh PRT3IE Interrupt Enables[7:0] RW : 00
1,00h PRT0DM0 Drive Mode 0[7:0] RW : 00
1,01h PRT0DM1 Drive Mode 1[7:0] RW : FF
1,04h PRT1DM0 Drive Mode 0[7:0] RW : 00
1,05h PRT1DM1 Drive Mode 1[7:0] RW : FF
1,08h PRT2DM0 Drive Mode 0[7:0] RW : 00
1,09h PRT2DM1 Drive Mode 1[7:0] RW : FF
1,0Ch PRT3DM0 Drive Mode 0[7:0] RW : 00
1,0Dh PRT3DM1 Drive Mode 1[7:0] RW : FF
0,10h PRTxDR Data[7:0] RW : 00
0,11h PRTxIE Interrupt Enables[7:0] RW : 00
1,10h PRTxDM0 Drive Mode 0[7:0] RW : 00
1,11h PRTxDM1 Drive Mode 0[7:0] RW : 00