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enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H

107

C Slave

15.3.3

I2C_CFG Register

The I

C Configuration Register (I2C_CFG) is used to set the

basic operating modes, baud rate, and selection of inter-
rupts. The bits in this register control baud rate selection and
optional interrupts. The values are typically set once for a
given configuration. The bits in this register are all RW.

Bit 6: PSelect.

Pin Select. With the default value of zero,

the I

C pins are P1[7] for clock and P1[5] for data. When this

bit is set, the pins for I

C switch to P1[1] for clock and P1[0]

for data. You cannot change this bit while the Enable bit is
set. However, the PSelect bit may be set at the same time
as the enable bits. The two sets of pins used on I

C are not

equivalent. The default set, P1[7] and P1[5], are the pre-
ferred set. The alternate set, P1[1] and P1[0], are provided
so that I

C may be used with 8-pin enCoRe V devices.

If In-System Serial Programming (ISSP) is used and the
alternate I

C pin set is also used, you must consider the

interaction between the enCoRe V Test Controller and the
I

C bus. The interface requirements for ISSP must be

reviewed to ensure that they are not violated.

Even if ISSP is not used, pins P1[1] and P1[0] respond dif-
ferently than other I/O pins to a POR or XRES event. After
an  XRES  event,  both  pins  are  pulled  down  to  ground  by
going into the resistive zero drive mode before reaching the
High-Z  drive  mode.  After  a  POR  event,  P1[0]  drives  out  a
one, then goes to the resistive zero state for some time, and
finally  reaches  the  High-Z  drive  mode  state.  After  POR,
P1[1] goes into a resistive zero state for a while before going
to the High-Z drive mode.

Bit 4: Stop IE.

Stop Interrupt Enable. When this bit is set, a

slave can interrupt upon Stop detection. The status bit asso-
ciated with this interrupt is the Stop Status bit in the

I2C_SCR Register

. When the Stop Status bit transitions

from ‘0’ to ‘1’, the interrupt is generated. It is important to
note that the Stop Status bit is not automatically cleared.
Therefore, if it is already set, no new interrupts are gener-
ated until it is cleared by firmware.

Bits 3 and 2: Clock Rate[1:0].

These bits offer a selection

of three sampling and bit rates. All block clocking is based
on the SYSCLK input, which is nominally12 MHz or 6 MHz.
The sampling rate and the baud rate are determined as fol-
lows:

■

Sample Rate = SYSCLK/Prescale Factor

■

Baud Rate = 1/(Sample Rate x Samples per Bit)

When clocking the input with a frequency other than 6-/12-
MHz (for example, clocking the device with an external
clock), the baud rates and sampling rates scale accordingly.
Whether the block works in a Standard Mode or Fast Mode
system depends upon the sample rate.

The sample rate must be sufficient to resolve bus events,
such as Start and Stop conditions. See the Philips Semicon-
ductors (now NXP Semiconductors) I

C-Bus Specification,

version 2.1, for minimum start and stop hold times.

Bit 0: Enable.

When the slave is enabled, the block gener-

ates an interrupt upon any Start condition and an address
byte that it receives indicating the beginning of an I

C trans-

fer. When operating as a slave, the block is clocked from an
external  master.  Therefore,  the  block  works  at  any  fre-
quency up to the maximum defined by the currently selected
clock rate. The internal clock is only used in slave mode, to
ensure that there is adequate setup time from data output to
the  next  clock  upon  the  release  of  a  slave  stall.  When  the
Enable bit is ‘0’, the block is held in reset and all status is
cleared. Block enable is synchronized to the SYSCLK clock
input  (

see “Timing Diagrams” on page 111

). If the block is

enabled when there is an I

C transaction already on the I

bus, an erroneous start is detected if SCL is high and SDA is
low.  (SDA  in  this  case  is  low  because  of  a  data/ack  bit.)
Thus,  to  avoid  this  erroneous  start  detection,  enable  the
block  only  when  the  bus  is  idle  (SCL  and  SDA  are  high
when idle) or only when both SCL and SDA are low.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Access

0,D6h