enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
97
Digital Clocks
Figure 14-1. Overview of enCoRe V Clock Sources
14.1.3
External Clock
In addition to the IMO clock source, an externally supplied
clock may be selected as the device master clock (see
Pin P1[4] is the input pin for the external clock. If P1[4] is
selected as the external clock source, the drive mode of the
pin must be set to High-Z (not High-Z Analog).
An external clock with a frequency between 1 MHz and
24 MHz can be supplied. The reset state of the EXTCLKEN
bit is ‘0’. With this setting, the device always boots up under
the control of the IMO. The system cannot be started from a
reset with the external clock.
When the EXTCLKEN bit is set, the external clock becomes
the source for the internal clock tree, SYSCLK, which drives
most enCoRe V device clocking functions. All external and
internal signals, including the ILO or ECO low frequency
clock, are synchronized to this clock source. Note that there
is no glitch protection in the device for an external clock.
User should ensure that the external clock is glitch free. See
device datasheet for the clock specifications.
In applications where XRES is used when in external clock
mode, care must be taken to switch the clock source to IMO
before entering the low-power modes. The clock source can
be switched back to external clock upon completion of wake
up either in the interrupt routine or in the main code. Failure
to do this will cause the device to hang up.
An example implementation is shown here:
OSC_CR2 &= ~0x04; /* Disconnect External
Clock and connect IMO to SYSCLK*/
M8C_Sleep; /* Entering sleep */
asm("nop");
OSC_CR2 |= 0x04; /*Connect External Clock to
SYSCLK */
14.1.3.1
Switch Operation
Switching between the IMO and the external clock is done in
firmware at any time and is transparent to the user.
Switch timing depends upon whether the CPU clock divider
is set for divide by 1, or divide by 2 or greater. If the CPU
clock divider is set for divide by 2 or greater, as shown in
, the setting of the EXTCLKEN bit occurs shortly
after the rising edge of SYSCLK. The SYSCLK output is
then disabled after the next falling edge of SYSCLK, but
before the next rising edge. This ensures a glitch free transi-
tion and provides a full cycle of setup time from SYSCLK to
output disable. After the current clock selection is disabled,
the enable of the newly selected clock is double synchro-
nized to that clock. After synchronization, on the subsequent
negative edge, SYSCLK is enabled to output the newly
selected clock.
In the 12 MHz case, as shown in
, the assertion
of IOW_ and thus the setting of the EXTCLKEN bit occurs
on the falling edge of SYSCLK. Because SYSCLK is already
low, the output is immediately disabled. Therefore, the setup
time from SYSCLK to disable is one-half SYSCLK.
SYSCLK
CPUCLK
SLEEP
Internal
Main
Oscillator
(IMO)
IMO Trim Register
CLK32K
EXTCLK
P1[4]
(EXTCLK Input)
IMO_TR[7:0]
OSC_CR2[2]
Clock Divider
OSC_CR0[2:0]
Sleep Clock Divider
OSC_CR0[4:3]
2
6
2
9
2
12
2
15
Slow IMO Option
CPU_SCR1[4:3]
1
2
4
8
16
32
128
256
ILO Trim Register
Internal Low
Speed
Oscillator
(ILO)
ILO_TR[7:0]
