enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
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4. RAM Paging
This chapter explains the enCoRe V device’s use of RAM Paging and its associated registers. For a complete table of the
RAM paging registers, refer to the
Summary Table of the Core Registers on page 24
. For a quick reference of all enCoRe V
registers in address order, refer to the
Register Reference chapter on page 163
4.1
Architectural Description
The M8C is an 8-bit CPU with an 8-bit memory address bus.
The memory address bus allows the M8C to access up to
256 bytes of SRAM, to increase the amount of available
SRAM and preserve the M8C
language. The
enCoRe V device has 1K and 2K bytes of SRAM with eight
pages of memory architecture.
To take full advantage of the paged memory architecture of
the enCoRe V device, you use several registers and man-
age two CPU_F register bits. However, the power-on-reset
(POR) value for all of the paging registers and CPU_F bits is
zero. This places the enCoRe V device in a mode identical
to devices with only 256 bytes of SRAM. There is no need to
understand all of the paging registers to take advantage of
the additional SRAM available in some devices. To use the
additional SRAM pages, modify the memory paging logic
reset state.
The memory paging architecture consists of five areas:
■
Stack Operations
■
Interrupts
■
MVI Instructions
■
Current Page Pointer
■
Indexed Memory Page Pointer
The first three of these areas do not depend upon the
CPU_F register's PgMode bits and are covered in the sub-
sections after Basic Paging. The function of the last two
depend upon the CPU_F PgMode bits and are covered last.
4.1.1
Basic Paging
To increase the amount of SRAM, the M8C accesses mem-
ory page bits. The memory page bits are located in the
CUR_PP register and allow selection of one of eight SRAM
pages. In addition to setting the page bits, Page mode is
enabled by setting the CPU_F[7] bit. If Page mode is not
enabled, the page bits are ignored and all non-stack mem-
ory access is directed to Page 0.
After Page mode is enabled and the page bits are set, all
instructions that operate on memory access the SRAM page
indicated by the page bits. The exceptions to this are the
instructions that operate on the stack and the
MVI
instruc-
tions:
PUSH
,
POP
,
LCALL
,
RETI
,
RET
,
CALL
, and
MVI
. See
the description of
and
for
a more detailed discussion.
Figure 4-1. Data Memory Organization
4.1.2
Stack Operations
As mentioned previously, the paging architecture's reset
state puts the enCoRe Vin a mode identical to that of a 256-
byte device. Therefore, upon reset, all memory accesses
are to Page 0. The SRAM page that stack operations use is
determined by the value of the three least significant bits
(LSb) of the Stack Page Pointer register (STK_PP). Stack
operations have no dependency on the PgMode bits in the
CPU_F register. Stack operations are those that use the
Stack Pointer (SP) to calculate their affected address. Refer
Page 0
SRAM
256 Bytes
ISR
Page 6
SRAM
256 Bytes
Page 5
SRAM
256 Bytes
Page 3
SRAM
256 Bytes
Page 2
SRAM
256 Bytes
Page 1
SRAM
256 Bytes
Page 7
SRAM
256 Bytes
Page 4
SRAM
256 Bytes
00h
FFh
