Cypress CY8C28 series, Техническое справочное руководство

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CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G 361
Digital Blocks
17.2.6 DxCxxIN Registers
The Digital Basic/Communications Type B Block Input Reg-
isters (DxCxxIN) are used to select the data and clock
inputs.
These registers are common to all functional types, except
the SPIS. The SPIS is unique in that it has three function
inputs and one function output defined. Refer to the
DxCxxOU registers.
The input registers are eight bits and consist of two 4-bit
fields to control each of the 16-to-1 Clock and Data input
muxes. The meaning of these fields depends on the exter-
nal clock and data connections, which is context specific.
See
Table 17-25 .
Bits 7 to 4: Data Input[3:0]. These bits control the data
input.
Bits 3 to 0: Clock Input[3:0]. These bits control the clock
input.
* The Dead Band reference input does not use the auxiliary input mux. It is
hardwired to be the primary output of the previous block.
** For CRC computation, the input data is a serial data stream synchronized
to the clock. For PRS mode, this input should be forced to logic 0.
For additional information, refer to the DxCxxIN register on
page 224 .
17.2.7 DxCxxOU Registers
The Digital Basic/Communications Type B Block Output
Registers (DxCxxOU) are used to control the connection of
digital block outputs to the available row interconnect and
control clock resynchronization.
When the selected function is SPI Slave (SPIS), the AUXEN
and AUX IO bits change meaning, and select the input
source and control for the Slave Select (SS_) signal.
The Digital Block Output register is common to all functional
types, except the SPIS. The SPIS function is unique in that it
has three function inputs and one function output defined.
When the Aux IO Enable bit is '0', the Aux IO Select bits are
used to select one of four inputs from the auxiliary data input
mux to drive the SS_ input. Alternatively, when the Aux IO
Enable bit is a '1', the SS_ signal is driven directly from the
value of the Aux IO Select[0] bit. Thus, the SS_ input can be
controlled in firmware, eliminating the need to use an addi-
tional GPIO pin for this purpose. Regardless of how the SS_
bit is configured, a SPIS block has the auxiliary row output
drivers forced off; and therefore, the auxiliary output is not
available in this block.
The following table enumerates the Primary and Auxiliary
outputs that are defined for a given block function. Most
functions have two outputs defined (the exception is the SPI
Slave, which has only one). One or both of these outputs
can optionally be enabled for output. When output, these
signals can be routed to other block inputs through row or
global interconnect, or output to chip pins.
Add. Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
1,xxh DxCxxIN 4, 3, 2, 1 Data Input[3:0] Clock Input[3:0] RW : 00
LEGEND
xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers,
refer to the “Digital Register Summary” on page 312 .
Table 17-25. Digital Block Input Definitions
Function
Inputs
DATA CLK Auxiliary
Timer Capture CLK N/A
Counter Enable CLK N/A
Dead Band Kill CLK Reference *
CRCPRS Serial Data ** CLK N/A
SPIM MISO CLK N/A
SPIS MOSI SCLK SS_
Transmitter N/A 8X Baud CLK N/A
Receiver RXD 8X Baud CLK N/A
Add. Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
1,xxh DxCxxOU 3, 2 AUXCLK AUXEN AUX IO Select[1:0] OUTEN Output Select[1:0] RW : 00
LEGEND
xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers,
refer to the “Digital Register Summary” on page 312 .