Cypress CY8C28 series, Техническое справочное руководство

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348 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
Digital Blocks
17.2 Register Definitions
The following registers are associated with the Digital Blocks and listed in address order. Note that there are two banks of reg-
isters associated with the PSoC device. Bank 0 encompasses the user registers (Data and Control registers, and Interrupt
Mask registers) for the device and Bank 1 encompasses the Configuration registers for the device. Refer to the
“Bank 0 Reg-
isters” on page 127 and the “Bank 1 Registers” on page 218 for a quick reference of PSoC registers in address order.
Each register description that follows has an associated register table showing the bit structure for that register. Depending on
how many digital rows your PSoC device has (see the Rows column in the register tables below), only certain bits are acces-
sible to be read or written (refer to the table titled
“PSoC Device Characteristics” on page 311 ). The bits that are grayed out
throughout this manual are reserved bits and are not detailed in the register descriptions that follow. Reserved bits should
always be written with a value of ‘0’.
The Digital Block registers in this chapter are organized by function, as presented in Table 17-10 . To reference timing dia-
grams associated with the digital block registers, see “Timing Diagrams” on page 363 . For a complete table of digital block
registers, refer to the “Summary Table of the Digital Registers” on page 312 .
Data and Control Registers
The following table summarizes the Data and Control registers, by function type, for the digital blocks.
Table 17-10. Digital Block Data and Control Register Definitions
Function
Type
DR0 DR1 DR2 CR0 CR1
Function Access Function Access Function Access Function Access Function Access
Timer Down Counter R * Period W Capture/Compare RW Control RW Control RW
Counter Down Counter R * Period W Compare RW Control RW Control RW
Dead Band Down Counter R * Period W N/A N/A Control RW Control RW
PWMDBL Down Counter R * Period W Compare RW Control RW Control RW
CRCPRS LFSR R * Polynomial W Seed RW Control RW Control RW
SPIM Shifter N/A TX Buffer W RX Buffer R Control/Status RW ** Control RW
SPIS Shifter N/A TX Buffer W RX Buffer R Control/Status RW ** Control RW
TXUART Shifter N/A TX Buffer W N/A N/A Control/Status RW ** N/A N/A
RXUART Shifter N/A N/A N/A RX Buffer R Control/Status RW ** N/A N/A
DSM Subtract R * Init-Phase W Density RW Control RW Control RW
LEGEND
* In Timer, Counter, Dead Band, CRCPRS, PWMDBL, and DSM functions, a read of the DR0 register returns 00h and transfers DR0 to DR2.
** In the Communications functions, control bits are read/write accessible and status bits are read only accessible.