Error Registers
3-11
Table 3-5 Miscellaneous Register (Continued)
Name
Bits
Type
Initial
State Description
ITINTR
<7:4>
R, W1C
0
Interval timer interrupt
pending – one bit per CPU.
Pin irq<2> is asserted to the
CPU corresponding to a 1 in
this field.
RES
<3:2>
MBZ, RAZ
0
Reserved.
CPUID
<1:0>
RO
-
ID of the CPU performing the
read.
Содержание AlphaServer DS20
Страница 8: ......
Страница 50: ......
Страница 90: ......
Страница 122: ...4 32 AlphaServer DS20 Service Manual 4 16 CD ROM Removal and Replacement Figure 4 15 Removing CD ROM PKW0519 97...
Страница 124: ...4 34 AlphaServer DS20 Service Manual 4 17 Floppy Removal and Replacement Figure 4 16 Removing Floppy 1 PK1401 98...
Страница 132: ......
Страница 144: ......
Страница 158: ......