
Description of Operation
4-2
ADSP-BF59x Blackfin Processor Hardware Reference
Features
The Blackfin architecture provides a two-level interrupt processing
scheme:
• The core event controller (CEC) runs in the
CCLK
clock domain. It
interacts closely with the program sequencer and manages the event
vector table (EVT). The CEC processes not only core-related inter-
rupts such as exceptions, core errors, and emulation events; it also
supports software interrupts.
• The system interrupt controller (SIC) runs in the
SCLK
clock
domain. It masks, groups, and prioritizes interrupt requests sig-
nalled by on-chip or off-chip peripherals and forwards them to the
CEC.
Description of Operation
The following sections describe the operation of the system interrupts.
Events and Sequencing
The processor employs a two-level event control mechanism. The proces-
sor SIC works with the CEC to prioritize and control all system
interrupts. The SIC provides mapping between the many peripheral inter-
rupt sources and the prioritized general-purpose interrupt inputs of the
core. This mapping is programmable, and individual interrupt sources can
be masked in the SIC.
The CEC of the processor manages five types of activities or events:
• Emulation
• Reset
• Nonmaskable interrupts (NMI)
Содержание ADSP-BF59x Blackfin
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