Analog Devices ADSP-BF59x Blackfin, Справочник по аппаратуре, Страница: 443 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 12-45
Two Wire Interface Controller
TWI FIFO Receive Data Double Byte
Register (TWI_RCV_DATA16)
The
TWI_RCV_DATA16
register holds a 16-bit data value read from the FIFO
buffer. To reduce interrupt output rates and peripheral bus access times, a
double byte receive data access can be performed. Two data bytes can be
read, effectively emptying the receive FIFO buffer with a single access.
The data is read in little endian byte order as shown in Figure 12-30
where byte 0 is the first byte received and byte 1 is the second byte
received. With each access, the receive status (
RCVSTAT
) field in the
TWI_FIFO_STAT
register is updated to indicate it is empty. If an access is
performed while the FIFO buffer is not full, the read data is unknown and
the existing FIFO buffer data and its status remains unchanged.
Figure 12-29. TWI FIFO Receive Data Single Byte Register
Figure 12-30. Receive Little Endian Byte Order
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TWI FIFO Receive Data S ingle Byte Register (TWI_RCV_DATA 8 )
All bits are RO.
RCVDATA 8 [7:0] (Receive
FIFO 8 -Bit Data)
Reset = 0x0000
RECEIVE DATA REGISTER
B1 B0
TRANSMISSION LINE
B1 B0