Analog Devices ADSP-BF59x Blackfin, Справочник по аппаратуре, Страница: 209 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 6-5
Dynamic Power Management
automatically by the system control ROM function (
bfrom_SysControl()
)
as described in “System Control ROM Function” on page 6-22 .
Core Clock/System Clock Ratio Control
Table 6-2 describes the programmable relationship between the VCO fre-
quency and the core clock. Table 6-3 shows the relationship of the VCO
frequency to the system clock. Note the divider ratio must be chosen to
limit the
SCLK
to a frequency specified in the processor data sheet. The
SCLK
drives all synchronous, system-level logic.
The divider ratio control bits,
CSEL
and
SSEL
, are in the PLL divide
(
PLL_DIV
) register. For information about this register, see “PLL_DIV
Register” on page 6-19 .
The reset value of
CSEL[1:0]
is 0x0, and the reset value of
SSEL[3:0]
is
0x4. These values can be reprogrammed at startup by the boot code.
By updating
PLL_DIV
with an appropriate value, you can change the
CSEL
and
SSEL
value dynamically. Note the divider ratio of the core clock can
never be greater than the divider ratio of the system clock. If the
PLL_DIV
register is programmed to illegal values, the
SCLK
divider is automatically
increased to be greater than or equal to the core clock divider.
Unlike writing the
PLL_CTL
register, the
PLL_DIV
register can be pro-
grammed at any time to change the
CCLK
and
SCLK
divide values without
entering the PLL programing sequence.
Table 6-2. Core Clock Ratio
Signal Name
CSEL[1:0] Divider Ratio
VCO/CCLK Example Frequency Ratios (MHz)
VCO
CCLK
00 1 300 300
01 2 300 150
10 4 400 100
11 8 400 50