Analog Devices ADSP-BF59x Blackfin, Справочник по аппаратуре, Страница: 215 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 6-11
Dynamic Power Management
For transitions to processor states, the text next to each transition arrow
shows either a processor event (hardware reset or wakeup event) or the
fields in the voltage regulator control register (
VR_CTL
) that must be
changed for the transition to occur.
For information about how to effect mode transitions, see “Programming
Operating Mode Transitions” on page 6-13 .
In addition to the mode transitions shown in Figure 6-2 , the PLL can be
modified while in active operating mode. Changes to the PLL do not take
effect immediately. As with operating mode transitions, the PLL program-
ming sequence must be executed for these changes to take effect (see
“Programming Operating Mode Transitions” on page 6-13 ).
• PLL disabled: In addition to being bypassed in the active mode, the
PLL can be disabled.
When the PLL is disabled, additional power savings are achieved
although they are relatively small. To disable the PLL, set the
PLL_OFF
bit in the
PLL_CTL
register, and then execute the PLL pro-
gramming sequence.
• PLL enabled: When the PLL is disabled, it can be re-enabled later
when additional performance is required.
The PLL must be re-enabled before transitioning to the full-on or
sleep operating modes. To re-enable the PLL, clear the
PLL_OFF
bit
in the
PLL_CTL
register, and then execute the PLL programming
sequence.
• New multiplier ratio: The multiplier ratio can also be changed
while in full-on mode.