Analog Devices ADSP-BF59x Blackfin, Справочник по аппаратуре, Страница: 565 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 14-59
SPORT Controller
When reading from the FIFO for both primary and secondary data, read
primary first, followed by secondary. DAB/peripheral bus reads must
match their size to the data word length. For word length up to and
including 16 bits, use a 16-bit read. Use a 32-bit read for word length
greater than 16 bits.
When receiving is enabled, data from the
DRPRI
pin is loaded into the RX
primary shift register, while data from the
DRSEC
pin is loaded into the RX
secondary shift register. At transfer completion of a word, data is shifted
into the RX hold registers for primary and secondary data, respectively.
Data from the hold registers is moved into the FIFO based on
RXSE
and
SLEN
.
The SPORT RX interrupt is generated when
RSPEN
= 1 and the RX FIFO
has received words in it. When the core processor has read all the words in
the FIFO, the RX interrupt is cleared. The SPORT RX interrupt is set
only if SPORT RX DMA is disabled; otherwise, the FIFO is read by
DMA reads.
If the program causes the core processor to attempt a read from an empty
RX FIFO, old data is read, the
RUVF
flag is set in the
SPORT_STAT
register,
and the SPORT error interrupt is asserted. The
RUVF
bit is a sticky bit and
is cleared only when the SPORT is disabled. To determine if the core can
access the RX registers without causing this error, first read the RX FIFO
status (
RXNE
in the
SPORT_STAT
register). The
RUVF
status bit is updated
even when the SPORT is disabled.
The
ROVF
status bit is set in the
SPORT_STAT
register when a new word is
assembled in the RX shift register and the RX hold register has not moved
the data to the FIFO. The previously written word in the hold register is
overwritten. The
ROVF
bit is a sticky bit; it is only cleared by disabling the
SPORT RX.