Analog Devices ADSP-BF59x Blackfin, Справочник по аппаратуре, Страница: 442 / 772

Register Descriptions
12-44 ADSP-BF59x Blackfin Processor Hardware Reference
FIFO buffer is not empty, the write is ignored and the existing FIFO buf-
fer data and its status remains unchanged.
TWI FIFO Receive Data Single Byte
Register (TWI_RCV_DATA8)
The
TWI_RCV_DATA8
register holds an 8-bit data value read from the FIFO
buffer. Receive data is read from the corresponding receive buffer in a
first-in first-out order. Although peripheral bus reads are 16 bits, a read
access to
TWI_RCV_DATA8
will access only one transmit data byte from the
FIFO buffer. With each access, the receive status (
RCVSTAT
) field in the
TWI_FIFO_STAT
register is updated. If an access is performed while the
FIFO buffer is empty, the data is unknown and the FIFO buffer status
remains indicating it is empty.
Figure 12-27. Transmit Little Endian Byte Order
Figure 12-28. TWI FIFO Transmit Data Double Byte Register
B1
TRANSMIT DATA REGISTER
B0
TRANSMISSION LINE
B1 B0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TWI FIFO Transmit Data Double Byte Register (TWI_XMT_DATA16)
All bits are WO. This register always reads as 0x0000.
XMTDATA16[15:0] (Transmit
FIFO 16-Bit Data)
Reset = 0x0000