Analog Devices ADSP-BF59x Blackfin, Справочник по аппаратуре, Страница: 58 / 772

Clock Signals
1-16 ADSP-BF59x Blackfin Processor Hardware Reference
The timer is clocked by the system clock (
SCLK
), at a maximum frequency
of f
SCLK
.
Clock Signals
The processor can be clocked by an external crystal, a sine wave input, or a
buffered, shaped clock derived from an external clock oscillator.
This external clock connects to the processor’s
CLKIN
pin. The
CLKIN
input
cannot be halted, changed, or operated below the specified frequency dur-
ing normal operation. This clock signal should be a TTL-compatible
signal.
The core clock (
CCLK
) and system peripheral clock (
SCLK
) are derived from
the input clock (
CLKIN
) signal. An on-chip Phase Locked Loop (PLL) is
capable of multiplying the
CLKIN
signal by a user-programmable (5× to
64×) multiplication factor (bounded by specified minimum and maxi-
mum
VCO
frequencies). The default multiplier is 6×, but it can be modified
by a software instruction sequence. On-the-fly frequency changes can be
made by simply writing to the
PLL_DIV
register.
All on-chip peripherals are clocked by the system clock (
SCLK
). The system
clock frequency is programmable by means of the
SSEL[3:0]
bits of the
PLL_DIV
register.
Dynamic Power Management
The processor provides four operating modes, each with a different perfor-
mance/power profile. In addition, dynamic power management provides
the control functions to dynamically alter the processor core supply volt-
age to further reduce power dissipation. Control of clocking to each of the
peripherals also reduces power consumption.