4-8
IM 704610-01E
•
The setting for the gate time and number of blocks during block sampling is restricted such
that maximum number of samples that can be acquired by the instrument is not exceeded.
For details, see the Note in section 4.7.
Loading the Measured Values When D-to-C High Speed Calculation is ON
•
When D-to-C high speed calculation is ON, the measured values of the measurement clock
delimited every 2 ms are moving-summed over the gate time range, and the results are
displayed or DC-output (see section 7.1).
•
Meter indication, numeric display, and DC output are updated as shown below.
•
The SSTart and STOP communication commands cannot be executed when D-to-C high
speed calculation is ON.
Example of Display/Output Updating When the Gate Time is 8 ms
•
Meter indication and DC output
2 ms
2 ms
2 ms
2 ms
2 ms
2 ms
2 ms
2 ms
2 ms
2 ms
Gate time of 8 ms
Gate time of 8 ms
Gate time of 8 ms
Updates the display/output of the moving-summed result every 2 ms.
The summing time is the same as the gate time.
RF signal
•
Numeric display
2 ms 2 ms 2 ms 2 ms 2 ms
2 ms 2 ms 2 ms 2 ms 2 ms
2 ms 2 ms 2 ms 2 ms
Gate time of
8 ms
Gate time of
8 ms
Gate time of
8 ms
Gate time of
8 ms
Gate time of
8 ms
RF signal
RF signal
RF signal
Approx. 150 ms
Approx. 150 ms
Updates the display of the moving-summed result
approximately every 150 ms.
The summing time is the same as the gate time.
•
The setting for the gate time and number of blocks during block sampling is restricted such
that the maximum number of samples that can be acquired by the instrument is not
exceeded. For details, see the Note in section 4.7.
4.5 Setting the Gate Time