10-36
IM 704610-01E
10.3 Status Report
Status Byte Operation
When bit 6 of the status byte is 1, a service request
occurs. When a bit other than 6 is set to 1, bit 6 also
becomes 1 (if the corresponding service request
enable register is set to 1).
For example, if an event occurs and the logical AND of
the standard event register and the corresponding
enable register becomes a “1”, then bit 5 (ESB) is set
to “1.” In this case, if bit 5 of the service request enable
register is 1, bit 6 (MSS) is set to 1, and a service is
requested of the controller. Also, by reading the status
byte, you can confirm what type of event occurred.
Reading the Status Byte
The following two methods can be used to read the
contents of the status byte.
Query Using *STB?
If you send a query using *STB?, bit 6 becomes MSS.
Therefore, MSS is read out. After it is read out, none
of the bits of the status byte are cleared.
Serial Poll
When serial poll is performed, bit 6 becomes RQS.
Therefore, RQS is read out. After it is read out, only
RQS is cleared. MSS cannot be read out using serial
poll.
Clearing the Status Byte
There is no way to forcibly clear all bits of the status
byte. The following shows which actions clear which
bits.
Query Using *STB?
No bits are cleared.
When Serial Poll Is Performed
Only the RQS bit is cleared.
When the *CLS Command Is Received
When the *CLS command is received, the status byte
itself is not cleared, but the contents of the standard
event register and other registers that have an effect
on each bit are cleared. As a result, the corresponding
status byte bits are cleared. However, the output
queue cannot be cleared using the *CLS command, so
bit 4 (MAV) of the status byte is not affected.
However, when sending the *CLS command directly
after the program message terminator, the output
queue is also cleared.
10.3.3
Standard Event Register
Standard Event Register
URQ
6
PON
7
5
4
3
2
1
0
CME EXE DDE QYERQCOPC
Bit 7
PON (Power ON) ON (power)
Set to 1 when the instrument’s power is turned ON.
Bit 6
URQ (User Request)
Unused (always 0)
Bit 5
CME (Command Error)
Set to 1 when a syntax error is found in a command.
Example: Mistaken command name, or a 9
occurring within octal data.
Bit 4
EXE (Execution Error)
Set to 1 when the command syntax is correct but the
command cannot be executed in the current condition.
Example: Parameters are out of range.
Bit 3
DDE (Device Dependent Error)
Set to 1 when a command could not be executed due
to an instrument-internal problem other than a
command syntax error or command execution error.
Bit 2
QYE (Query Error)
Set to 1 when a query command was sent but either
the output queue is empty or data was lost.
Example: No response data, or data was lost due
to an overflowing output queue.
Bit 1
RQC (Request Control)
Unused (always 0)
Bit 0
OPC (Operation Complete)
Set to “1” when the operation specified by the *OPC
command (see section 10.2) has been completed.
Bit Masking
To mask bits of the standard event register so that they
are not a factor of bit 5 (ESB) of the status byte, the
corresponding bits of the standard event enable
register are set to 0.
For example, to have ESB not be set to 1 even when
bit 2 (QYE) is masked and a query error occurs, set bit
2 of the standard event enable register to 0. This is
done using the *ESE command. Also, you can query
whether each bit of the standard event enable register
is 1 or 0 using the *ESE? command. See section 10.2
for information on the *ESE command.