Byte 44 ... 47
Byte
Bit 7 ... Bit 0
44
2. edge evaluation (1 = edge detected, 0 = no edge detected). Here the last
presence of an edge since the last read access to the
FA1
register is stored.
After a read access to this register (in the module) the register is not reset.
n
Bit 0: Status I+0.0
n
...
n
Bit 7: Status I+0.7
45
Edge evaluation
n
Bit 0: Status I+1.0
n
...
n
Bit 7: Status I+0.7
46...47
reserved
For guarantee of consistency of a µs ticker entry to the
1. edge evaluation
(FA1) the
2.
edge evaluation
(FA2) serves for. The consistency is ensured only if the appropriate bit of
the
FA2
is "0". Since the last read access if more than one edge change took place, the
corresponding bit of
edge lost
(FV) is set. Here the µs ticker entry contains the time of the
last edge.
Example:
Byte
+1
+0
FA1
4
0
1
1
0
0
0
1
0
0
1
0
1
1
1
1
0
FV
8
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
...
FA2
44
0
0
1
1
0
0
0
0
0
0
0
1
0
0
1
0
The consistent µs ticker entries can be determined by logical bit operations:
FA1
AND
NOT
FA2
Result
bit operation:
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
Output address range
Byte
Bit 7 ... Bit 0
0
Control output channel (1 = set, 0 = set back)
n
Bit 0: Status Q+0.0
n
...
n
Bit 7: Status Q+0.7
1
Control output channel (1 = set, 0 = set back)
n
Bit 0: Status Q+1.0
n
...
n
Bit 7: Status Q+1.7
VIPA System 300S
Digital Modules FAST - SPEED-Bus
323-1BH70 - DIO 16xDC 24V 0.5A > Parameterization
HB140 | SM-DIO | | en | Rev. 16-43
113