ACD1
16
PIN
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Vcc-RTC
XTAL2
EXTAL2
Vss-RTC
MD1
MD2
NMI
IRQ0/IRL0_/PTH[0]
IRQ1/IRL1_/PTH[1]
IRQ2/IRL2_/PTH[2]
IRQ3/IRL3_/PTH[3]
IRQ4/PTH[4]
VEPWC
VCPWC
MD5
/BREQ
/BACK
VssQ
CKIO2
VccQ
D31/PTB[7]
D30/PTB[6]
D29/PTB[5]
D28/PTB[4]
D27/PTB[3]
D26/PTB[2]
D25/PTB[1]
D24/PTB[0]
VssQ
D23/PTA[7]
VccQ
D22/PTA[6]
D21/PTA[5]
D20/PTA[4]
Vss
D19/PTA[3]
Vcc
D18/PTA[2]
D17/PTA[1]
D16/PTA[0]
D15
VssQ
D14
VccQ
D13
D12
D11
D10
D9
D8
D7
D6
VssQ
D5
VccQ
D4
D3
D2
D1
D0
A0
A1
A2
VssQ
A3
VccQ
A4
A5
A6
A7
A8
A9
A10
A11
VssQ
A12
VccQ
A13
A14
A15
A16
A17
A18
A19
A20
VssQ
A21
VccQ
A22
A23
Vss
A24
Vcc
A25
BS_/PTK[4]
RD_
WE0_/DQMLL
WE1_/DQMLU/WE
WE2_/DQMUL/ICIORD_/PTK[6]
VssQ
WE3_/DQMUU/ICIOWR_/PTK{7}
VccQ
RD/WR_
PTE[7]/PCC0RDY/AUDSYNC_
/CS0
/CS2
/CS3
/CS4/PTK[2]
/CS5/CE1A_/PTK[3}
/CS6/CE1B_
CE2A_/PTE[4]
CE2B_/PTE[5]
AFE_HC1/USB1d_DPLS/PTK[0]
AFE_RLYCNT_/USB1d_DMNS/PTK[1]
VssQ
AFE_SCLK/USB1d_TXDPLS
VccQ
PTM[7]/PTINT[7]/AFE_FS/USB1d_RCV
PTM[6]/PTINT[6]/AFE_RXIN/USB1d_SPEED
PTM[5]/PTINT[5]/AFE_TXOUT/USB1d_TXSE0
-
-
-
-
-
-
-
I
I
I
I
I
O
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
I/O
-
I/O
I/O
I/O
-
I/O
-
I/O
I/O
I/O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
O
-
O
O
O
-
O
-
O
O
-
-
-
O
O
O
O
O
O
O
-
I
-
I
I
I
Power supply for RTC (1.9V)
Not in use (XTAL for internal RTC)
Power supply for RTC (0V)
Clock mode setting
Not in use (Non-maskable interrupt request)
External interrupt request
VEE control pin for LCD panel
VCC control pin for LCD panel
Big endian setting
Not in use (bus request)
Bus acknowledge
VssQ
System clock output
VccQ
Data bus
VssQ
Data bus
VccQ
Data bus
Vss
Data bus
Vcc
Data bus
VssQ
Data bus
VccQ
Data bus
VssQ
Data bus
VccQ
Data bus
Address bus
VssQ
Address bus
VccQ
Address bus
VssQ
Address bus
VccQ
Address bus
VssQ
Address bus
VccQ
Address bus
Vss
Address bus
Vcc
Address bus
Not connected (bus cycle start signal)
Read strobe
Write 0 signal
Write 1 signal
Write 2 signal
VssQ
Write 3 signal
VccQ
Read/Write
I/O
Chip Select 0
Chip Select 2
Chip Select 3
Chip Select 4
Chip Select 5
Chip Select 6
Output port (SWP50 Reset)
Output port (PLG Board Reset)
SPD DATA
SPD CL
VssQ
Not in use (USB1 D+ transmission)
VccQ
Not in use
PIN
NO.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
PTM[4]/PINT[4]/AFE_RDET_/USB1d_TXDMNS
Reserved/USB1d_SUSPEND
USB1_ovr_crnt/USBF_VBUS
USB2_ovr_crnt_
RTS2_/USB1d_TXENL
PTE[2]/USB1_pwr_en
PTE[1]/USB2_pwr_en
CKE/PTK[5]
/RAS3/PTJ[0]
Reserved/PTJ[1]
Reserved//CAS/PTJ[2]
VssQ
Reserved/PTJ[3]
VccQ
Reserved/PTJ[4]
Reserved/PTJ[5]
Vss
PTD[5]/CL1
Vcc
PTD[7]/DON
PTE[6]/M_DISP
PTE[3]/FLM
PTE[0]/TDO
PCC0RESET/DRACK0
PCC0DRV_/DACK0_
/WAIT
/RESETM
/ADTRG/PTH[5]
/IOIS16/PTG[7]
/ASEMD0
PTG[5]/ASEBRKAK_
PTG[4]
PCC0BVD2/PTG[3]/AUDATA[3]
PCC0BVD1/PTG[2]/AUDATA[2]
Vss
PCC0CD2/PTG[1]/AUDATA[1]
Vcc
PCC0CD1/PTG[0]/AUDATA[0]
VssQ
PTF[7]/PINT[15]/TRST_
VccQ
PTF[6]/PINT[14]/TMS
PTF[5]/PINT[13]/TDI
PTF[4]/PINT[12]/TCK
PTF[3]/PINT[11]/Reserved
PCCREG_/PTF[2]/Reserved
PCC0VS1_/PTF[1]/Reserved
PCC0VS2_/PTF[0]/Reserved
MD0
Vcc-PLL1
CAP1
Vss-PLL1
Vss-PLL2
CAP2
Vcc-PLL2
PCC0WAIT_/PTH[6]/AUDCK
Vss
Vcc
XTAL
EXTAL
LCD15/PTM[3]/PINT[10]
LCD14/PTM[2]/PINT[9]
LCD13/PTM[1]/PINT[8]
LCD12/PTM[0]
STATUS0/PTJ[6]
STATUS1/PTJ[7]
CL2/PTH[7]
VssQ
CKIO
VccQ
TxD0/SCPT[0]
SCK0/SCPT[1]
TxD_SIO/SCPT[2]
SIOMCLK/SCPT[3]
TxD2/SCPT[4]
SCK_SIO/SCPT[5]
SIOFSYNC/SCPT[6]
RxD0/SCPT[0]
RxD_SIO/SCPT[2]
Vss
RxD2/SCPT[4]
Vcc
SCPT[7]/CTS2_/IRQ5
LCD11/PTC[7]/PINT[3]
LCD10/PTC[6]/PINT[2]
LCD9/PTC[5]/PINT[1]
VssQ
LCD8/PTC[4]/PINT[0]
VccQ
LCD7/PTD[3]
LCD6/PTD[2]
LCD5/PTC[3]
LCD4/PTC[2]
LCD3/PTC[1]
LCD2/PTC[0]
LCD1/PTD[1]
LCD0/PTD[0]
DREQ0_/PTD[4]
LCK/UCLK/PTD[6]
/RESETP
CA
MD3
MD4
/Scan_testen
Avcc_USB
USB1_P
USB1_M
Avss_USB
USB2_P
USB2_M
Avcc_USB
Avss
AN[2]/PTL[2]
AN[3]/PTL[3]
AN[4]/PTL[4]
AN[5]/PTL[5]
Avcc
AN[6]/PTL[6]/DA[1]
AN[7]/PTL[7]/DA[0]
Avss
I
O
I
-
O
O
O
O
O
O
O
-
O
-
O
O
-
O
-
O
O
O
O
O
O
-
-
I
I
-
I
I
I
-
I
-
I
-
I
-
I
I
I
I
I
I
I
-
-
-
-
-
-
-
I
-
-
-
-
I
I
I
I
O
O
O
-
-
-
O
O
O
O
O
O
O
i
i
-
i
-
I
O
O
O
-
O
-
O
O
O
O
O
O
O
O
I
I
-
-
-
-
-
-
IO
IO
-
IO
IO
-
-
I
I
I
I
-
I
O
-
Not in use
USB function VBUS
USB2_HOST2 over current detection
Not in use
USB1 voltage control
USB2 voltage control
Enable (SDRAM)
RAS for SDRAM
Not in use
CAS for SDRAM
VssQ
Output port (DAC Reset)
VccQ
Output port (SIO Reset)
Output port (DAC Mute)
Vss
LCD line clock
Vcc
LCD DISPLAY ON
LCD alternater
LCD frame line marker
JTAG (test data output)
DMA request acceptance
DMA acknowledge
Hardware wait request
Manual reset request
Analog A/D trigger
Not in use
Vss
Not in use
Vcc
Not in use
VssQ
Not in use
VccQ
Not in use
Clock mode setting
Power supply for Vcc_PLL1 - PLL1(1.9V)
External capacitance for CAP1 _ PLL1
Power supply for Vss_PLL1 _ PLL1(0V)
Power supply for Vss_PLL2 _ PLL2 (0V)
External capacitance for CAP2 _ PLL2
Power supply for Vcc_PLL2 _ PLL2 (1.9V)
Not in use
Vss
Vcc
Clock oscillator
External clock
Not in use
Input port (Flash ROM RY/BY)
Output port (Flash ROM write protect)
Output port (Flash ROM ACC)
LCD clock output
VssQ
System clock input/output (for SDRAM)
VccQ
Output port for SCI
Not in use
Output port for SCI
Not in use
Receiving data 0
Not in use
Vss
Receiving data 2
Vcc
Not in use
Output port (PLG CLOCK ON/OFF)
Not in use
VssQ
Not in use
VccQ
LCD DATA7
LCD DATA6
LCD DATA5
LCD DATA4
LCD DATA3
LCD DATA2
LCD DATA1
LCD DATA0
DMA request
USB clock
Power on reset request
Hardware standby request
Bus width setting for area0
Test pin (fixed to 3.3V)
USB analog power supply (3.3V)
USB1 data input/output (+)
USB1 data input/output (-)
USB analog power supply (0V)
USB2 data input/output (+)
USB2 data input/output (-)
USB analog power supply (3.3V)
A/D analog power supply (0V)
AD converter input
A/D analog power supply (3.3V)
AD converter input
DA converter output (LCD contrast)
A/D analog power supply (0V)
I/O
I/O
NAME
FUNCTION
FUNCTION
NAME
HD6417727F160CV
(X2890B00)
CPU
CPU: IC002
