Yamaha ACD1, Service Manual

Page: 15 / 125

15
ACD1
PIN
NO.
I/O FUNCTION NAME
PIN
NO.
I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MDIO
MDC
RXD3/PHYAD1
RXD2/PHYAD2
RXD1/PHYAD3
RXD0/PHYAD4
VDDIO
GND
RXDV/PCS_LPBK
RXC
RXER/ISO
GND
VDDC
TXER
TXC/REF_CLK
TXEN
TXD0
TXD1
TXD2
TXD3
COL/RMII
CRS/RMII_BTB
GND
VDDIO
I/O
I
O
O
O
O
–
–
O
O
O
–
–
I
I/O
I
I
I
I
I
O
O
–
–
Management Data Input / Output.
Management Data clockt.
Receive Data 3.
Receive Data 2.
Receive Data 1.
Receive Data 0.
Power
Ground
Receive Data Valid.
Receive Clock.
Receive Error.
Ground
Power
Transmit Error.
Transmit Clock.
Transmit Enable input.
Transmit data 0.
Transmit data 1.
Transmit data 2.
Transmit data 3.
Collision (Detect).
Carrier Sense.
Ground
Power 25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48 INT#/PHYAD0
LED0/TEST
LED1/SPD100
LED2/DUPLEX
LED3/NWAYEN
PD#
VDDRX
RX-
RX+
FXSD/FXEN
GND
GND
REXT
VDDRCV
GND
TX-
TX+
VDDTX
GND
GND
XO
XI
VDDPLL
RST#
O
O
O
O
O
I
–
I
I
O
–
–
I
–
–
O
O
–
–
–
O
I
–
I
Management interface (Mll) interrupt out.
Link/Activity LED.
Speed LED.
Full-duplex LED.
Collsion LED.
Power down
Power
Receive input.
Fiber Mode Enable / signal detect in fiber Mode.
Ground.
External resistor (6.49kW) connects to REXT and GND.
Power
Ground
Transmit outputs.
Power
Ground.
XTAL Feedback.
Crystal Oscillator.
Power
Chip Reset.
KSZ8721SL
(X5621A00)
PHY
(Physical Layer)
ENT2: IC109
PIN
NO.
I/O FUNCTION NAME
PIN
NO.
I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TDI
A5
A6
A7
GND0
VCCO0
A8
A9
A10
A11
TCK
VCC
GND
A12
A13
A14
A15
CLK1/I
CLK2/I
B0
B1
B2
B3
B4
I
I/O
I/O
I/O
–
–
I/O
I/O
I/O
I/O
I
–
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Test data in
Input/Output
Ground
Power 3.3 V
Input/Output
Test clock input
Power 3.3 V
Ground
Input/Output
CLK input / Input
Input/Output
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48 TMS
B5
B6
B7
GND1
VCCO1
B8
B9
B10
B11
TDO
VCC
GND
B12
B13
B14
B15/GOE1
CLK3/I
CLK0/I
A0/GOE0
A1
A2
A3
A4
I
I/O
I/O
I/O
–
–
I/O
I/O
I/O
I/O
O
–
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Test mode select
Input/Output
Ground
Power 3.3 V
Input/Output
Test data out
Power 3.3 V
Ground
Input/Output
Input/Output / Global output enable input
CLK input / Input
Input/Output / Global output enable input
Input/Output
LC4032V-75TN48C
(X7109A00)
CPLD
(Complex Programmable Logic Device)
IC014
IC014
CPU: IC014
LSI PIN DESCRIPTION
（LSI 端子機能表）
LC4032V-75TN48C
(X7109A0R)
CPLD
(Complex Programmable Logic Device) .............................15
HD6417727F160CV
(X2890B00)
CPU
...............................................................................................16
YTD442-RZ
(X7197A00)
VNP1
...........................................................................................................17
KSZ8721SL
(X5621A00)
PHY
(Physical Layer) .................................................................................15