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ACD1
CPU CIRCUIT DIAGRAM (ACD1) 002
CPU CIRCUIT DIAGRAM (ACD1) 002
5
28CC1-2001031028-2
: Not installed
(未実装)
REAL TIME CLOCK
CPLD
AND GATE
AND GATE
INVERTER
INVERTER
SYSTEM RESET
(検出電圧 3.0 V)
Detection voltage: 3.0 V
for CPLD
bypass capacitors
AND