MTi 1-series User Manual
Xsens MTi User Manual Repository
Hardware Integration Manual
Copyright © 2021 Xsens
Page 86
I
2
C address
ADD2
ADD1
ADD0
0x69
1
0
1
0x6A
1
1
0
0x6B
(default)
1
1
1
SPI
For the SPI interface, PSEL1 can be left floating or pulled-up to VDDIO and the PSEL0 pin needs
to be connected to GND, as shown below.
Connections (SPI interface)
UART
For the UART full-duplex interface, the PSEL1 and PSEL0 pins need to be connected to GND, as
shown below. The UART full-duplex communications mode can be used without hardware flow
control. In this case, the CTS line needs to be tied low (GND) to make the MTi 1-series transmit.
For the UART half‑duplex interface, PSEL1 needs to be connected to GND and the PSEL0 pin
must be left floating (see table above).
