Xilinx VC707, User Manual

Page: 2 / 100

VC707 Evaluation Board www.xilinx.com UG885 (v1.2) February 1, 2013
Notice of Disclaimer
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum
extent permitted by applicable law: (1) Materials are made available “AS IS” and with all faults, Xilinx hereby DISCLAIMS ALL
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether
in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising
under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or
consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action
brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.
Xilinx assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update. You may not
reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and
conditions of the Limited Warranties which can be viewed at
http://www.xilinx.com/warranty.htm ; IP cores may be subject to warranty and
support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any
application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications:
http://www.xilinx.com/warranty.htm#critapps .
© Copyright 2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Vivado, Virtex, Zynq, and other designated brands included
herein are trademarks of Xilinx in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG.
HDMI, HDMI logo, and High-Definition Multimedia Interface are trademarks of HDMI Licensing LLC. All other trademarks are the property
of their respective owners.
Revision History
The following table shows the revision history for this document.
Date Version Revision
03/05/12 1.0 Initial Xilinx release.
10/08/12 1.1 Chapter 1, VC707 Evaluation Board Features : In Table 1-1 , notes for J37 changed to
Samtec ASP_134486_01. The board photo in Figure 1-2 was replaced. In Table 1-3 , GPGA
(U1) Bank 32 was deleted. A note was added about the user clock for Figure 1-10 . In
Table 1-15 , FPGA pin AN1 changed to AM4 and pin AN2 changed to AM3. In SGMII
GTX Transceiver Clock Generation, page 37 , 25 MHz LVDS clock changed to 125 MHz
LVDS clo
ck. The
Figure 1-10 title also
changed from 25 MHz to 125 MHz. In
Table 1-23 ,
pin AR42 changed to AT42. In Figure 1-33 , switching regulator supply voltage UG63 for
MGTVCCAUX was updated. In Table 1-29 , device type PTD08D021W (V
OUT
A) power
rail voltage changed to 1.80V. In Table 1-32 , values for rail number 3 changed. In
Appendix C, Master UCF Listing , the entire listing was replaced. Appendix G,
Regulatory and Compliance Information now includes a link to the Declaration of
Conformity and markings for waste electrical and electronic equipment (WEEE),
restriction of hazardous substances (RoHS), and CE compliance.
02/01/13 1.2 Updated VC707 Board Features , Table 1-1 , Virtex-7 XC7VX485T-2FFG1761C FPGA ,
FPGA Configuration , USB JTAG , System Clock (SYSCLK_P and SYSCLK_N) , HDMI
Video Output , I
2
C Bus , Table 1-15 , User I/O , Table 1-26 , Power Management , and VITA
57.1 FMC2 HPC Connector (Partially Populated) . Updated Figure 1-5 , Figure 1-16 , and
Figure 1-25 . Updated paragraph following Table 1-4 , Figure 1-7 , Figure 1-19 , Figure 1-20 ,
and Table 1-24 . Added CPU Reset Pushbutton , User Rotary Switch , User SMA , and PCIe
Form Factor Board TI Power System Cooling . Added Table 1-27 and Table 1-28 .
Replaced PTD08D021W with PTD08D210W in Table 1-29 . Added third paragraph to the
introduction in Appendix C, Master UCF Listing . Added UG483 and removed NXP
Semiconductors in References . Added second paragraph to the introduction in
Appendix G, Regulatory and Compliance Information .