VC707 Evaluation Board
89
UG885 (v1.2) February 1, 2013
VC707 Board UCF Listing
NET DDR3_A9 LOC = C19 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L1P_T0_38
NET DDR3_A1 LOC = B19 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L1N_T0_38
NET DDR3_A5 LOC = A16 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L2P_T0_38
NET DDR3_A12 LOC = A15 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L2N_T0_38
NET DDR3_A0 LOC = A20 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L3P_T0_DQS_38
NET DDR3_A3 LOC = A19 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L3N_T0_DQS_38
NET DDR3_A11 LOC = B17 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L4P_T0_38
NET DDR3_A4 LOC = A17 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L4N_T0_38
NET DDR3_A10 LOC = B21 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L5P_T0_38
NET DDR3_A13 LOC = A21 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L5N_T0_38
NET DDR3_A7 LOC = C18 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L6P_T0_38
NET VTTVREF LOC = B18 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L6N_T0_VREF_38
NET DDR3_A6 LOC = D20 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L7P_T1_38
NET DDR3_A2 LOC = C20 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L7N_T1_38
NET DDR3_A14 LOC = F17 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L8P_T1_38
NET DDR3_A15 LOC = E17 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L8N_T1_38
NET DDR3_BA0 LOC = D21 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L9P_T1_DQS_38
NET DDR3_BA1 LOC = C21 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L9N_T1_DQS_38
NET DDR3_BA2 LOC = D18 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L10P_T1_38
NET DDR3_A8 LOC = D17 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L10N_T1_38
NET DDR3_CLK1_P LOC = G19 | IOSTANDARD=DIFF_SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L11P_T1_SRCC_38
NET DDR3_CLK1_N LOC = F19 | IOSTANDARD=DIFF_SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L11N_T1_SRCC_38
NET SYSCLK_P LOC = E19 | IOSTANDARD=LVDS; # Bank 38 VCCO - VCC1V5_FPGA - IO_L12P_T1_MRCC_38
NET SYSCLK_N LOC = E18 | IOSTANDARD=LVDS; # Bank 38 VCCO - VCC1V5_FPGA - IO_L12N_T1_MRCC_38
NET DDR3_CLK0_P LOC = H19 | IOSTANDARD=DIFF_SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L13P_T2_MRCC_38
NET DDR3_CLK0_N LOC = G18 | IOSTANDARD=DIFF_SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L13N_T2_MRCC_38
NET DDR3_CKE0 LOC = K19 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L14P_T2_SRCC_38
NET DDR3_CKE1 LOC = J18 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L14N_T2_SRCC_38
NET DDR3_WE_B LOC = F20 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L15P_T2_DQS_38
NET DDR3_RAS_B LOC = E20 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L15N_T2_DQS_38
NET DDR3_CAS_B LOC = K17 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L16P_T2_38
NET DDR3_S0_B LOC = J17 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L16N_T2_38
NET DDR3_S1_B LOC = J20 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L17P_T2_38
NET DDR3_ODT0 LOC = H20 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L17N_T2_38
NET DDR3_ODT1 LOC = H18 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L18P_T2_38
NET DDR3_TEMP_EVENT LOC = G17 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L18N_T2_38
#NET 10N481 LOC = P18 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L19P_T3_38
#NET VTTVREF LOC = P17 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L19N_T3_VREF_38
NET 10N483 LOC = M17 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L20P_T3_38
NET 10N484 LOC = L17 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L20N_T3_38
NET 10N485 LOC = N19 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L21P_T3_DQS_38
NET 10N486 LOC = N18 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L21N_T3_DQS_38
NET 10N487 LOC = M19 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L22P_T3_38
NET 10N488 LOC = M18 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L22N_T3_38
NET 10N489 LOC = P20 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L23P_T3_38
NET 10N490 LOC = N20 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L23N_T3_38
NET 10N491 LOC = L20 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L24P_T3_38
NET 10N492 LOC = L19 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_L24N_T3_38
#NET VRP_38 LOC = K20 | IOSTANDARD=SSTL15; # Bank 38 VCCO - VCC1V5_FPGA - IO_25_VRP_38
#NET VRN_39 LOC = J16 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_0_VRN_39
NET DDR3_D30 LOC = C16 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L1P_T0_39
NET DDR3_D26 LOC = B16 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L1N_T0_39
NET DDR3_D24 LOC = B14 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L2P_T0_39
NET DDR3_DM3 LOC = A14 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L2N_T0_39
NET DDR3_DQS3_P LOC = C15 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L3P_T0_DQS_39
NET DDR3_DQS3_N LOC = C14 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L3N_T0_DQS_39
NET DDR3_D28 LOC = D13 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L4P_T0_39
NET DDR3_D25 LOC = C13 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L4N_T0_39
NET DDR3_D31 LOC = D16 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L5P_T0_39
NET DDR3_D27 LOC = D15 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L5N_T0_39
NET DDR3_D29 LOC = E12 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L6P_T0_39
#NET VTTVREF LOC = D12 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L6N_T0_VREF_39
#NET 10N563 LOC = F16 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L7P_T1_39
NET DDR3_D16 LOC = E15 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L7N_T1_39
NET DDR3_D19 LOC = E14 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L8P_T1_39
NET DDR3_D17 LOC = E13 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L8N_T1_39
NET DDR3_DQS2_P LOC = H16 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L9P_T1_DQS_39
NET DDR3_DQS2_N LOC = G16 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L9N_T1_DQS_39
NET DDR3_D21 LOC = G12 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L10P_T1_39
NET DDR3_DM2 LOC = F12 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L10N_T1_39
NET DDR3_D18 LOC = F15 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L11P_T1_SRCC_39
NET DDR3_D22 LOC = F14 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L11N_T1_SRCC_39
NET DDR3_D23 LOC = G14 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L12P_T1_MRCC_39
NET DDR3_D20 LOC = G13 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L12N_T1_MRCC_39
#NET 10N497 LOC = H15 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L13P_T2_MRCC_39
NET DDR3_D14 LOC = H14 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L13N_T2_MRCC_39
NET DDR3_D11 LOC = J13 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L14P_T2_SRCC_39
NET DDR3_D10 LOC = H13 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L14N_T2_SRCC_39
NET DDR3_DQS1_P LOC = K12 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L15P_T2_DQS_39
NET DDR3_DQS1_N LOC = J12 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L15N_T2_DQS_39
NET DDR3_DM1 LOC = K15 | IOSTANDARD=SSTL15; # Bank 39 VCCO - VCC1V5_FPGA - IO_L16P_T2_39
