Xilinx VC707, User Manual

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VC707 Evaluation Board www.xilinx.com 69
UG885 (v1.2) February 1, 2013
Feature Descriptions
Table 1-32 defines the voltage and current values for each power rail controlled by the
UCD9248 PMBus controller at address 54 (U64).
FPGA Cooling Fan Operation
The FPGA cooling fan control circuit has its PWM signal wired to a dual-use FPGA
Bank 15 pin BA37. After configuration, this pin is expected to be toggled by user-provided
fan speed control IP to control fan speed.
FPGA U1 pin BA37 is alternately an unused BPI flash memory address pin (A28). During
FPGA configuration in BPI mode, the BPI flash memory address lines are driven. The BA37
pin is held low during BPI configuration and thus the fan PWM signal is not active. The
FPGA U1 cooling fan is off during the FPGA BPI configuration process.
After configuration is complete, the dual-use FPGA pin BA37 is available for use by
user-provided fan speed control IP.
References
More information about the power system components used by the VC707 board are
available from the Texas Instruments digital power website
[Ref 9] .
PCIe Form Factor Board TI Power System Cooling
If the power modules on the VC707 board are operating at moderate to high current levels
(due to a customer design), the modules can generate substantial heat, which can cause
them to shut down without warning. The power module shutdown then turns off the
FPGA on the development board. Refer to the Virtex-7 FPGA VC707 Evaluation Kit Master
Answer Record in
Appendix F : Further Resources for more information.
XADC Analog-to-Digital Converter
7 series FPGAs provide an analog front end XADC block. The XADC block includes a dual
12-bit, 1 MSPS analog-to-digital convertor (ADC) and on-chip sensors. See
UG480 , 7 Series FPGAs XADC Dual 12-Bit 1MSPS Analog-to-Digital Converter User Guide
for
Table 1-32: Power Rail Specifications for UCD9248 PMBus Controller at Address 54
Shutdown Threshold
(1)
Rail
Number
Rail
Name
Schematic
Rail Name
No
min
a
l V
OUT
(V)
PG O
n
T
h
resh
old
(V)
PG O
ff
Thresh
old
(V)
On De
la
y (ms)
Rise
Tim
e
(m
s)
Off Dela
y
(ms)
F
a
ll T
ime (
m
s)
V
OUT
Over F
a
ult (V)
I
OUT
Over F
a
ult (A)
T
e
mp
Over F
a
u
lt (°
C)
1 Rail #1 VCCAUX_IO 2 1.8 1.7 0 5 2 1 2.3 10.41 90
2 Rail #2 VCC_BRAM 1 0.9 0.85 0 5 9 1 1.15 10.41 90
3 Rail #3 MGTVCCAUX 1.8 1.62 1.53 0 5 7 1 2.07 10.41 90
4 Rail #4 VCC1V8_FPGA 1.8 1.62 1.53 0 5 5 1 2.07 10.41 90
Notes:
1. The values defined in these columns are the voltage, current, and temperature thresholds that cause the regulator to shut down if
the value is exceeded.