Xilinx VC707, User Manual

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VC707 Evaluation Board www.xilinx.com 43
UG885 (v1.2) February 1, 2013
Feature Descriptions
LCD Character Display (16 x 2)
[ Figure 1-2 , callout 19 ]
A 2-line by 16-character display is provided on the VC707 board ( Figure 1-19 ).
The character display runs at 5.0V and is connected to the FPGA's 1.8V HP bank 15
through a TI TXS0108E 8-bit bidirectional voltage level translator (U33).
Figure 1-20 shows
the LCD interface circuit.
The VC707 board base board uses a male Samtec MTLW-107-07-G-D-265 2x7 header (J23)
with 0.025-inch square posts on 0.100-inch centers for connecting to a Samtec
SLW-107-01-L-D female socket on the LCD display panel assembly. The LCD header
shown in
Figure 1-21 . When the LCD is not installed, the J31 header pins listed in
Table 1-23 are available for use as GPIO.
X-Ref Target - Figure 1-19
Figure 1-19: LCD Display
UG885_c1_19_020612
LCD Display (16 x 2)
X-Ref Target - Figure 1-20
Figure 1-20: LCD Interface Circuit
UG885_c1_20_020612
LCD Contrast
Potentiometer
LCD_RW
LCD_DB4
LCD_DB6
LCD_RS
LCD_E
NC
NC
LCD_DB5
LCD_DB7
9
8 7
6 5
4 3
2
10
1
12
14 11
13 LCD_VEE
GND
VCCB
B1
B2
B3
B4
B6
B7
GND
A3
A8
OE
A4
A5
A7
A6
B5
A1
A2
B8
VCCA
19
20
18
17
16
14
13
11
4
9
10
5
6
8
7
15
1
3
12
2
U33
VCC1V5_FPGA
LCD_E_LS
LCD_RW_LS
LCD_DB4_LS
LCD_DB5_LS
LCD_DB6_LS
LCD_DB7_LS
LCD_RS_LS
NC
LCD_RS
LCD_DB7
LCD_DB6
LCD_DB5
LCD_DB4
LCD_RW
LCD_E
NC
TXS0108E 8-Bit
Bidirectional
Voltage Level
Translator
J23
GND
VCC5V0
R118
6.81k
Ω
R232
2 k
Ω
NC
NC
VCC5V0
C54
0.1
μ
F 25V
X5R
GND
VCC5V0
C53
0.1
μ
F 25V
X5R
GND
GND