Xilinx VC707, User Manual

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VC707 Evaluation Board www.xilinx.com 11
UG885 (v1.2) February 1, 2013
Feature Descriptions
DDR3 Memory
[ Figure 1-2 , callout 2 ]
The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module
(SODIMM). It provides volatile synchronous dynamic random access memory (SDRAM)
for storing user code and data.
• Part number: MT8JTF12864HZ-1G6G1 (Micron Technology)
• Supply voltage: 1.5V
• Datapath width: 64 bits
• Data rate: Up to 1,600 MT/s
The DDR3 interface is implemented across I/O banks 37, 38, and 39. Each bank is a 1.5V
high-performance bank having a dedicated DCI VRP/N resistor connection. An external
0.75V reference VTTREF is provided for data interface banks 37 and 39. Any interface
connected to these banks that requires a reference voltage must use this FPGA voltage
reference. The connections between the DDR3 memory and the FPGA are listed in
Table 1-4 .
Bank 35 VADJ_FPGA 1.8V (default)
Bank 36 FMC1_VIO_B_M2C Variable
Bank 37 VCC1V5_FPGA 1.5V
Bank 38 VCC1V5_FPGA 1.5V
Bank 39 VCC1V5_FPGA 1.5V
Notes:
1. The VADJ_FPGA rail can support up to 1.8V due to FPGA HP
bank connections to FMC. For more information on
VADJ_FPGA see Power Management, page 65 .
Table 1-3: I/O Voltage Rails (Cont’d)
FPGA (U1)
Bank
Power Supply Rail
Net Name
Voltage
Table 1-4: DDR3 Memory Connections to the FPGA
FPGA (U1)
Pin
Net Name
J1 DDR3 Memory
Pin Number Pin Name
A20 DDR3_A0 98 A0
B19 DDR3_A1 97 A1
C20 DDR3_A2 96 A2
A19 DDR3_A3 95 A3
A17 DDR3_A4 92 A4
A16 DDR3_A5 91 A5
D20 DDR3_A6 90 A6
C18 DDR3_A7 86 A7
D17 DDR3_A8 89 A8