Xilinx VC707, User Manual

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20 www.xilinx.com VC707 Evaluation Board
UG885 (v1.2) February 1, 2013
Chapter 1: VC707 Evaluation Board Features
Figure 1-5 shows the USB 2.0 ULPI Transceiver circuitry.
SD Card Interface
[ Figure 1-2 , callout 5 ]
The VC707 board includes a secure digital input/output (SDIO) interface to provide
user-logic access to general purpose nonvolatile SDIO memory cards and peripherals. The
SD card slot is designed to support 50 MHz high speed SD cards.
The SDIO signals are connected to I/O bank 13 which has its VCCO set to 1.8V. A TI
TXB0108 8-bit bidirectional voltage-level translator (U31) is used between the FPGA and
the SD card connector (U29).
Figure 1-6 shows the connections of the SD card interface on
the VC707 board.
X-Ref Target - Figure 1-5
Figure 1-5: USB 2.0 ULPI Transceiver
U S B 33 20
U S B 2.0
ULPI Tr a n s ceiver
2
4
3
U 8
1
5
DATA2
25
26
17
DATA1
DATA0
NXT
CLKOUT
REFCLK
XO
6
7
10
12
11
9
1 3
DATA7
NC
REF S EL1
DATA6
DATA5
DATA4
DATA 3
19
1 8
2 3
21
24
20
VDD 33 _P
VBAT
RBIA S
ID
DP
DM
14
15
S PK_L
REF S EL2
33
CTR_GND
U S B_ S M S C_NXT
U S B_ S M S C_DATA0
U S B_ S M S C_DATA1
U S B_ S M S C_DATA2
U S B_ S M S C_DATA 3
U S B_ S M S C_DATA4
UG 88 5_c1_05_011 8 1 3
R2
27.4
Ω
J14
VCC1V 8
U S B_ S M S C_CLKOUT
VCC1V 8
Connector,
U S B Mini B
VBU S
D_N
GND
ID
D_P
J2
S HIELD
S HIELD
S HIELD
2
4
3
1
5
7
9
8
6
S HIELD
U S B_ S M S C_HEADER_N
U S B_ S M S C_HEADER_P
U S B_ S M S C_ID
3
1
2
GND
C 3 26
Not
In
s t a lled
+
J44
16
S PK_R
8
REF S EL0
U S B_ S M S C_DATA5
U S B_ S M S C_DATA6
NC
U S B_ S M S C_DATA 3
NC
NC
1
2 X1
24.000 MHz
3 0 PPM
GND
C 3 05
1 8 pF
C 3 04
1 8 pF
TP S 2051B
Power-Di s tri bu tion
S witch
EN
IN
OC_B
U17
OUT
GND
5
4
1
2
3
R 3 2 3
1 M
Ω
R167
0
Ω
R27 3
0
Ω
L25 Ferrite 220
C104
0.1
μ
F
L26 Ferrite 220
C247
0.1
μ
F
GND
VCC5V0
CPEN
VCC 3 V 3
R22 3
10 k
Ω
R2
Not
In
s t a lled
GND
J1 3
C272
150
μ
F
C179
1
μ
F
+
GND
22
VBU S
1
3
2
J45
R222
10.0 k
Ω
R291
1.00 k
Ω
U S B_ S M S C_VBU S _ S EL
U S B_ S M S C_REFCLK_OPTION
R249
DNP
VCC1V 8
3 0
VDD1 8
GND
C2 8 2
2.2
μ
F
R 3 2 3
1 M
Ω
3 2
VDDIO
2 8
VDD1 8
3 1
27
29
RE S ETB
S TP
DIR
U S B_ S M S C_DIR
U S B_ S M S C_ S TP
U S B_ S M S C_RE S ET
Def au lt = No j u mper
24 MHz
Def au lt =
No j u mper
Power from
U
S B ho s t (J2)
Def au lt =
j u mper pin s 1 - 2