W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 149 -
33. One ZQCS command can effectively correct a minimum of 0.5 % (ZQ Correction) of RON and R
TT
impedance error within 64 nCK for all speed bins assuming the maximum sensitivities specified in the
‘Output Driver Voltage and Temperature Sensitivity’ and ‘ODT Voltage and Temperature Sensitivity’
tables. The appropriate interval between ZQCS commands can be determined from these tables and
other application-specific parameters.
One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate)
and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The
interval could be defined by the following formula:
)
Vdriftrate
×
(VSens
+
)
Tdriftrate
×
(TSens
on
ZQCorrecti
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM
temperature and voltage sensitivities.
For example, if TSens = 1.5% /
C, VSens = 0.15% / mV, Tdriftrate = 1
C / sec and Vdriftrate = 15
mV/sec, then the interval between ZQCS commands is calculated as:
15)
×
(0.15
+
1)
×
(1.5
0.5
= 0.133 ≈ 128mS
34. Commands not requiring a locked DLL are all commands except Read, Read with Auto-Precharge and
Synchronous ODT.
35. Commands requiring a locked DLL are Read, Read with Auto-Precharge and Synchronous ODT.
36. A maximum of one regular plus eight posted refresh commands can be issued to any given DDR3L
SDRAM device meaning that the maximum absolute interval between any refresh command and the
next refresh command is 9 ×t
REFI
.
37. Parameter t
CK
(avg) is specified per its average value. However, it is understood that the relationship
between the average timing t
CK
(avg) and the respective absolute instantaneous timing t
CK
(abs) holds
all times.
38. t
CH
(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the
following falling edge.
39. t
CL
(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the
following rising edge.
40. t
DS
(base) and t
DH
(base) values are for a single-ended 1V/nS slew rate DQs (DQs are at 2V/nS for
DDR3L-1866 and DDR3L-2133) and 2V/nS DQS, DQS# differential slew rate. Note for DQ and DM
signals, V
REF(DC)
= V
REFDQ(DC)
. For input only pins except RESET#, V
REF(DC)
= V
REFCA(DC)
. See
section 10.16.5
“Data Setup, Hold and Slew Rate Derating”
on page 157.
41. t
IS
(base) and t
IH
(base) values are for 1V/nS CMD/ADD single-ended slew rate and 2V/nS CK, CK#
differential slew rate. Note for DQ and DM signals, V
REF(DC)
= V
REFDQ(DC)
. For input only pins except
RESET#, V
REF(DC)
= V
REFCA(DC)
. See section 10.16.4
“Address / Command Setup, Hold and
on page 150.
42. The setup and hold times are listed converting the base specification values (to which derating tables
apply) to V
REF
when the slew rate is 1 V/nS (DQs are at 2V/nS for DDR3L-1866 and DDR3L-2133).
These values, with a slew rate of 1 V/nS (DQs are at 2V/nS for DDR3L-1866 and DDR3L-2133), are for
reference only.
43. For definition of RTT turn-on time t
AON
See 8.19.2.2
on page 81.
44. For definition of RTT turn-off time t
AOF
See 8.19.2.2
on page 81.
45. There is no maximum cycle time limit besides the need to satisfy the refresh interval, t
REFI.
46. Actual value dependent upon measurement level definitions See Figure 41 -
“Method for calculating
t
WPRE
transitions and endpoints”
on page 59 and See Figure 42 -
“Method for calculating t
WPST
transitions and endpoints”
on page 59.
