Winbond W632GU6NB Series General Description Manual Download Page 134

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W632GU6NB

Publication Release Date: Aug. 20, 2018

Revision: A01

- 134 -

Definition for tJIT(cc) and tJIT(cc,lck)

JIT(cc)

is defined as the absolute difference in clock period between two consecutive clock cycles.

JIT(cc)

= Max of |{t

i +1

- t

}|.

JIT(cc)

defines the cycle to cycle jitter when the DLL is already locked.

JIT(cc,lck)

uses the same definition for cycle to cycle jitter, during the DLL locking period only.

JIT(cc)

and t

JIT(cc,lck)

are not subject to production test.

Definition for tERR(nper)

ERR

is defined as the cumulative error across n multiple consecutive cycles from t

CK(avg)

. t

ERR

is not

subject to production test.

10.15 Speed Bins

DDR3L SDRAM Speed Bins include t

, t

RCD

, t

RP,

and t

RAS

for each corresponding bin.

10.15.1 DDR3L-1333 Speed Bin and Operating Conditions

Speed Bin

DDR3L-1333

UNIT

NOTES

CL-nRCD-nRP

9-9-9

Part Number Extension

-15/15I/15J

Parameter

Symbol

Min.

Max.

Maximum operating frequency using maximum
allowed settings for Sup_CL and Sup_CWL

CKMAX



667

MHz

Internal read command to first data

13.5

(13.125)*

ACT to internal read or write delay time

RCD

13.5

(13.125)*



PRE command period

13.5

(13.125)*



ACT to ACT or REF command period

49.5

(49.125)*



ACT to PRE command period

RAS

9 * t

REFI

CL = 5

CWL = 5

CK(AVG)

3.0

3.3

1, 2, 3, 4, 6

CWL = 6, 7

CK(AVG)

Reserved

CL = 6

CWL = 5

CK(AVG)

2.5

3.3

1, 2, 3, 4, 6

CWL = 6, 7

CK(AVG)

Reserved

CL = 7

CWL = 5

CK(AVG)

Reserved

CWL = 6

CK(AVG)

1.875

< 2.5

1, 2, 3, 4, 6

(Optional)*

CWL = 7

CK(AVG)

Reserved

CL = 8

CWL = 5

CK(AVG)

Reserved

CWL = 6

CK(AVG)

1.875

< 2.5

1, 2, 3, 4, 6

CWL = 7

CK(AVG)

Reserved

CL = 9

CWL = 5, 6

CK(AVG)

Reserved

CWL = 7

CK(AVG)

1.5

< 1.875

1, 2, 3, 4

CL = 10

CWL = 5, 6

CK(AVG)

Reserved

CWL = 7

CK(AVG)

1.5

< 1.875

1, 2, 3, 4

Supported CL Settings

Sup_CL

5, 6,

(7)

, 8, 9, 10

nCK

Supported CWL Settings

Sup_CWL

5, 6, 7

nCK

Note:

Field value contents in blue font or parentheses are optional AC parameter and CL setting. Detail descriptions refer to note 10.

Summary of Contents for W632GU6NB Series

Page 1: ...r MR1 21 8 3 2 1 DLL Enable Disable 21 8 3 2 2 Output Driver Impedance Control 22 8 3 2 3 ODT RTT Values 22 8 3 2 4 Additive Latency AL 22 8 3 2 5 Write leveling 22 8 3 2 6 Output Disable 22 8 3 3 Mod...

Page 2: ...Violations 57 8 14 2 1 Motivation 57 8 14 2 2 Data Setup and Hold Violations 57 8 14 2 3 Strobe to Strobe and Strobe to Clock Violations 57 8 14 2 4 Write Timing Parameters 57 8 14 3 Write Data Mask 5...

Page 3: ...ded Input Signals 106 10 6 7 Slew Rate Definitions for Differential Input Signals 106 10 7 DC and AC Output Measurement Levels 107 10 7 1 Output Slew Rate Definition and Requirements 107 10 7 1 1 Sing...

Page 4: ...2 12I 12J 15 15I 15J speed grades 143 10 16 3 Timing Parameter Notes 147 10 16 4 Address Command Setup Hold and Derating 150 10 16 5 Data Setup Hold and Slew Rate Derating 157 11 Backward Compatible t...

Page 5: ...rt 40 C TCASE 105 C The W632GU6NB is designed to comply with the following key DDR3L SDRAM features such as posted CAS programmable CAS Write Latency CWL ZQ calibration on die termination and asynchro...

Page 6: ...r data data mask and differential strobe pairs Dynamic ODT mode for improved signal integrity and preselectable termination impedances during writes 2K Byte page size Packaged in VFBGA 96 Ball 7 5 x13...

Page 7: ...1 875 2 5 1 875 2 5 nS CL 8 CWL 6 tCK AVG 1 875 2 5 1 875 2 5 1 875 2 5 1 875 2 5 nS CL 9 CWL 7 tCK AVG 1 5 1 875 1 5 1 875 1 5 1 875 1 5 1 875 nS CL 10 CWL 7 tCK AVG 1 5 1 875 1 5 1 875 1 5 1 875 1...

Page 8: ...or lower SPD settings must be programmed to match For example DDR3L 1333 9 9 9 devices supporting down binning to DDR3L 1066 7 7 7 should program 13 125 nS in SPD bytes for tAAmin Byte 16 tRCDmin Byt...

Page 9: ...AP NC A12 BC BA1 VREFCA ZQ VDD VSS DQL5 VSS DQL3 VSSQ VSSQ DQU2 DQU6 VDDQ VSS VSSQ VDDQ VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD DQU7 VSS DQU1 DMU DQL0 DQSL DQSL DQL4 RAS CAS WE BA2 A0 A3 BA0 CS VDD...

Page 10: ...Data Mask DMU and DML are the input mask signals control the lower or upper bytes for write data Input data is masked when DMU DML is sampled HIGH coincident with that input data during a Write acces...

Page 11: ...tered in write data DQSU is paired with DQSU to provide differential pair signaling to the system during read and write data transfer DDR3L SDRAM supports differential data strobe only and does not su...

Page 12: ...A11 A12 A13 CS RAS CAS WE CK CK PREFETCH REGISTER ODT CONTROL COLUMN DECODER SENSE AMPLIFIER COLUMN DECODER COLUMN DECODER SENSE AMPLIFIER COLUMN DECODER CELL ARRAY BANK 5 ROW DECODER ROW DECODER ROW...

Page 13: ...Initialization Procedure 8 2 1 Power up Initialization Sequence The following sequence is required for POWER UP and Initialization 1 Apply power RESET is recommended to be maintained below 0 2 VDD all...

Page 14: ...e MRS command for MR2 provide Low to BA0 and BA2 High to BA1 7 Issue MRS Command to load MR3 with all application settings To issue MRS command for MR3 provide Low to BA2 High to BA0 and BA1 8 Issue M...

Page 15: ...ower up Initialization Sequence steps 2 to 11 3 The Reset sequence is now completed DDR3L SDRAM is ready for normal operation TIME BREAK DON T CARE Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk CK CK VDD VDDQ RESE...

Page 16: ...ss fields within the accessed mode register must be redefined when the MRS command is issued MRS command and DLL Reset do not affect array contents which mean these commands can be executed any time a...

Page 17: ...and Rtt_Nom DISABLED prior and or after MRS command ODTLoff 1 Figure 4 tMOD Timing The mode register contents can be changed using the same command and timing requirements during normal operation as l...

Page 18: ...0 0 0 0 0 0 Latency Reserved 7 8 9 11 10 5 6 BL A0 A1 0 0 0 1 8 Fixed BC4 or 8 on the fly A11 0 0 0 0 1 1 1 1 A10 0 0 1 1 0 0 1 1 A9 0 1 0 1 0 1 1 0 16 2 5 2 6 2 7 2 8 2 10 2 14 2 12 2 Mode A7 0 1 Nor...

Page 19: ...5 6 3 2 1 0 7 6 5 4 2 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 2 1 0 1 5 6 7 4 1 2 3 0 5 4 7 6 1 0 3 2 2 1 1 0 6 7 4 5 2 3 0 1 6 7 4 5 2 3 0 1 2 1 1 1 7 4 5 6 3 0 1 2 7 6 5 4 3 2 1 0 2 WRITE V V V 0 1 2...

Page 20: ...be used i e Read commands or ODT synchronous operations 8 3 1 5 Write Recovery The programmed WR value MR0 bits A9 A10 and A11 is used for the auto precharge feature along with tRP to determine tDAL W...

Page 21: ...t_Nom settings are allowed in Write Leveling Mode MR1 A 7 1 with MR1 A 12 0 only Rtt_Nom settings of RZQ 2 RZQ 4 and RZQ 6 are allowed 4 If Rtt_Nom is used during Writes only the values RZQ 2 RZQ 4 an...

Page 22: ...trolled by the sum of the AL and CAS Latency CL register settings Write Latency WL is controlled by the sum of the AL and CAS Write Latency CWL register settings A summary of the AL register options a...

Page 23: ...g temperature range ASR enable Manual SR Reference SRT BA0 A13 1 0 0 1 Reserved Reserved 1 1 1 1 0 0 1 1 1 A10 0 0 1 1 A9 0 1 0 1 Dynamic ODT off Write does not affect Rtt value Reserved RZQ 4 RZQ 2 A...

Page 24: ...on on page 57 8 3 3 3 Auto Self Refresh ASR and Self Refresh Temperature SRT DDR3L SDRAM must support Self Refresh operation at all supported temperatures Applications requiring Self Refresh operation...

Page 25: ...d synchronization 3 When MPR control is set for normal operation MR3 A 2 0 then MR3 A 1 0 will be ignored Figure 8 MR3 Definition 8 3 4 1 Multi Purpose Register MPR The Multi Purpose Register MPR func...

Page 26: ...tting of both CL 6 and CWL 6 DLL off mode will affect the Read data Clock to Data Strobe relationship tDQSCK but not the Data Strobe to Data relationship tDQSQ tQH Special attention is needed to line...

Page 27: ...timings from any MRS command are satisfied In addition if any ODT features were enabled in the mode registers when Self Refresh mode was entered the ODT signal must continuously be registered LOW unti...

Page 28: ...eatures are disabled in the mode registers when Self Refresh mode was entered ODT signal can be registered LOW or HIGH 6 Wait tXS then set MR1 bit A0 to 0 to enable the DLL 7 Wait tMRD then set MR0 bi...

Page 29: ...below the minimum operating frequency would require the use of DLL_on mode DLL_off mode transition sequence refer to section 8 7 DLL on off switching procedure on page 27 8 8 2 Frequency change durin...

Page 30: ...k frequency tCKSRX Notes 1 Applicable for both SLOW EXIT and FAST EXIT Precharge Power down 2 tAOFPD and tAOF must be satisfied and outputs High Z prior to T1 refer to ODT timing section for exact req...

Page 31: ...esides tDQSS tDSS and tDSH specification also needs to be fulfilled One way to achieve this is to combine the actual tDQSS in the application with an appropriate duty cycle and jitter on the DQS DQS s...

Page 32: ...MRS command performing the exit MR1 A7 0 may also change MR1 bits of A12 A9 A6 A5 A2 and A1 Since the controller levels one rank at a time the output of other ranks must be disabled by setting MR1 bit...

Page 33: ...s If feedback is driven only on one DQ the remaining DQs must be driven low as shown in above Figure and maintained at this state throughout the leveling procedure 2 MRS Load MR1 to enter write leveli...

Page 34: ...see Tb0 3 After the RTT is switched off disable Write Level Mode via MRS command see Tc2 4 After tMOD is satisfied Te1 any valid command may be registered MR commands may be issued after tMRD Td1 TIME...

Page 35: ...Multi Purpose Register The resulting operation when a RD or RDA command is issued is defined by MR3 bits A 1 0 when the MPR is enabled as shown in Table 6 When the MPR is enabled only RD or RDA comma...

Page 36: ...o 0 1 2 3 4 5 6 7 For Burst Chop 4 cases the burst order is switched on nibble base A 2 0b Burst order 0 1 2 3 A 2 1b Burst order 4 5 6 7 A 9 3 Don t care A10 AP Don t care A12 BC Selects burst chop m...

Page 37: ...order 0 1 2 3 BC4 100b Burst order 4 5 6 7 1b 11b RFU BL8 000b Burst order 0 1 2 3 4 5 6 7 BC4 000b Burst order 0 1 2 3 BC4 100b Burst order 4 5 6 7 Note Burst order bit 0 is assigned to LSB and the...

Page 38: ...rsts out the pre defined Read Calibration Pattern Memory controller repeats these calibration reads until read data capture at memory controller is optimized After end of last MPR read burst wait unti...

Page 39: ...Tc7 BA NOP NOP VALID 3 3 0 0 2 VALID 1 0 2 0 00 00 0 0 0 0 0 0 1 A 1 0 A 2 A 9 3 A10 AP A 11 A12 BC DQS DQS DQ RL tRP tMOD VALID 1 VALID VALID VALID VALID tMPRR tMOD Tc8 Tc9 Td NOTES 1 RD with BL8 eit...

Page 40: ...0 0 0 0 1 A 1 0 A 2 A 9 3 A10 AP A 11 A12 BC DQS DQS DQ RL VALID 1 VALID VALID VALID VALID tMPRR Tc8 Tc9 Td T10 3 VALID VALID 0 00 VALID 0 VALID 0 VALID 0 VALID 1 RL 0 2 0 2 READ 1 TIME BREAK DON T CA...

Page 41: ...0 A 2 A 9 3 A10 AP A 11 A12 BC DQS DQS DQ RL VALID 1 VALID VALID VALID VALID tMPRR tMOD Tc8 Tc9 Td T10 VALID VALID VALID VALID VALID 1 RL 0 2 1 4 READ 1 3 VALID 0 00 0 0 0 NOTES 1 RD with BC4 either...

Page 42: ...0 A 2 A 9 3 A10 AP A 11 A12 BC DQS DQS DQ RL VALID 1 VALID VALID VALID VALID tMPRR tMOD Tc8 Tc9 Td T10 VALID VALID VALID VALID VALID 1 RL 0 2 0 3 READ 1 3 VALID 0 00 0 0 0 NOTES 1 RD with BC4 either b...

Page 43: ...or the open row in all banks The bank s will be available for a subsequent row activation a specified time tRP after the PRECHARGE command is issued except in the case of concurrent auto precharge wh...

Page 44: ...2 Dout n data out from column n 3 NOP commands are shown for ease of illustration other commands may be valid at these times 4 BL8 setting activated by either MR0 A 1 0 00 or MR0 A 1 0 01 and A12 1 d...

Page 45: ...ime tDQSQ describes the latest valid transition of the associated DQ pins tQH describes the earliest invalid transition of the associated DQ pins Falling data strobe edge parameters tQSL describes the...

Page 46: ...obe tRPRE RL Measured to this point tRPST Notes 1 Within a burst rising strobe edge is not necessarily fixed to be always at tDQSCK min or tDQSCK max Instead rising strobe edge can vary between tDQSCK...

Page 47: ...2 Last data valid Dout n tRPRE tRPST NOP NOP NOP RL AL CL Dout n Dout n 1 Dout n 2 Dout n 4 Dout n 5 Dout n 6 Dout n 7 Dout n 1 Dout n 2 Dout n 4 Dout n 5 Dout n 6 Dout n 7 Dout n 1 Dout n 2 Dout n 3...

Page 48: ...LZ DQ by measuring the signal at two different voltages The actual voltage measurement points are not critical as long as the calculation is consistent The parameters tLZ DQS tLZ DQ tHZ DQS and tHZ DQ...

Page 49: ...cation tA tB tC tD t2 t1 tRPRE tRPRE_end tRPRE_begin VTT 0 VTT VTT Figure 27 Method for calculating tRPRE transitions and endpoints 8 13 2 5 tRPST Calculation The method for calculating differential p...

Page 50: ...or MR0 A 1 0 01 and A12 1 during READ commands at T0 and T4 Figure 29 READ BL8 to READ BL8 T0 T1 T3 T4 T5 T6 T7 T8 T9 T10 T11 CK CK Command 3 READ Address 4 NOP NOP NOP NOP READ NOP Bank Col n DQS DQ...

Page 51: ...0 and T4 Figure 31 READ BC4 to READ BC4 T0 T1 T3 T4 T5 T6 T7 T8 T9 T10 T11 CK CK Command 3 READ Address 4 NOP NOP NOP NOP NOP Bank Col n DQS DQS DQ 2 RL 6 Dout n Dout n 1 WL 5 tRPRE Dout n 2 Dout n 3...

Page 52: ...nd at T0 and WRITE command at T5 Bank Col n Bank Col b READ to WRITE Command Delay RL tCCD 2 2tCK WL TIME BREAK Figure 33 READ BC4 to WRITE BC4 OTF T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CK CK Command 3 RE...

Page 53: ...0 A 1 0 01 and A12 1 during READ command at T4 Figure 35 READ BC4 to READ BL8 OTF T0 T1 T3 T4 T5 T6 T7 T8 T9 T10 T11 CK CK Command 3 READ Address 4 NOP NOP NOP WRITE NOP DQS DQS DQ 2 RL 6 Dout n Dout...

Page 54: ...in b 1 Din b 2 Din b 7 T16 NOP NOP NOP tRPST tWPRE 4 clocks tWR tWTR TRANSITIONING DATA DON T CARE NOTES 1 RL 6 CL 6 AL 0 WL 5 CWL 5 AL 0 2 Dout n data out from column Din b data in from column b 3 NO...

Page 55: ...The minimum RAS cycle time tRC MIN from the previous bank activation has been satisfied Examples of Read commands followed by Precharge are show in Figure 38 and Figure 39 T0 T1 T2 T3 T4 T5 T6 T7 T8 T...

Page 56: ...Dout n Dout n 1 Dout n 2 Dout n 3 DQS DQS DQ BL4 Operation BL8 Operation tRP AL CL 2 12 T34 NOP tRTP Bank a Row b TRANSITIONING DATA DON T CARE NOTES 1 RL 26 CL 14 AL CL 2 2 Dout n data out from colu...

Page 57: ...0 on page 58 the relevant strobe edges for write burst A are associated with the clock edges T5 T5 5 T6 T6 5 T7 T7 5 T8 T8 5 Subsequent reads from that location might result in unpredictable read data...

Page 58: ...DSS tWPRE min tDSH tDQSS tDSH tDSH tDSH tWPST min tDQSH min tDSS tDSS tDSS tDSS tDSS tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL min tDQSS max Notes 1 BL8 WL 5 AL 0 CWL 5 2 Din n data in fro...

Page 59: ...for tWPRE specification VTT 0 V t1 tWPRE tWPRE_begin t2 tWPRE_end Figure 41 Method for calculating tWPRE transitions and endpoints 8 14 5 tWPST Calculation The method for calculating differential pul...

Page 60: ...1 0 00 or MR0 A 1 0 01 and A12 1 during WRITE command at T0 Figure 43 WRITE Burst Operation WL 5 AL 0 CWL 5 BL8 T0 T1 T5 T6 T9 T10 T11 T12 T13 T14 T15 CK CK Command 3 Address 4 DQS DQS DQ 2 Din n Din...

Page 61: ...ts with the first rising clock edge after the last write data shown at T7 Figure 45 WRITE BC4 to READ BC4 Operation T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Tn CK CK Command 3 Address 4 DQS DQS DQ 2 Din n Din n...

Page 62: ...ure 47 WRITE BC4 OTF to PRECHARGE Operation T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CK CK Command 3 Address 4 DQS DQS DQ 2 Din n Din n 2 Din n 3 Bank Col n WL 5 tWPRE Din n 1 tWPST 4 clocks Bank Col b T12 T...

Page 63: ...NOP NOP NOP NOP WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP TRANSITIONING DATA DON T CARE Bank Col b Bank Col n Figure 49 WRITE BC4 to WRITE BC4 OTF T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Din n Din n 2 Din n...

Page 64: ...CK CK Command 3 Address 4 DQS DQS DQ 2 WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP READ NOP NOP NOP NOP TRANSITIONING DATA DON T CARE Bank Col b Bank Col n 4 clocks Figure 51 WRITE BC4 to READ BC4 BL8...

Page 65: ...IONING DATA DON T CARE Bank Col b Bank Col n Din n 7 Din b 1 Din b 2 Din b tWR WL 5 tCCD Figure 53 WRITE BL8 to WRITE BC4 OTF T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Din n Din n 2 Din n 3 WL 5 tWPRE Din n 1...

Page 66: ...tponed during operation of the DDR3L SDRAM meaning that at no point in time more than a total of 8 Refresh commands are allowed to be postponed In case that 8 Refresh commands are postponed in a row t...

Page 67: ...ease Date Aug 20 2018 Revision A01 67 tRFC 8 REF Commands postponed tREFI 9 x tREFI t Figure 56 Postponing Refresh Commands Example tRFC 8 REF Commands pulled in tREFI 9 x tREFI t Figure 57 Pulling in...

Page 68: ...and that first Write operation or first Write Leveling Activity may not occur earlier than 512 nCK after exit from Self Refresh The DRAM initiates a minimum of one Refresh command internally within tC...

Page 69: ...um of one extra refresh command before it is put back into Self Refresh Mode T0 T1 T2 Ta0 Tb0 Tc0 Tc1 Td0 CK CK Command Tf0 Te0 VALID VALID VALID NOP SRE NOP NOP 1 VALID 2 VALID 3 SRX VALID VALID tRP...

Page 70: ...defined as tCPDED CKE_low will result in deactivation of command and address receivers after tCPDED has expired Table 7 Power Down Entry Definitions Status of DRAM MRS bit A12 DLL PD Exit Relevant Pa...

Page 71: ...ining open after completion of the precharge command Figure 59 Active Power Down Entry and Exit Timing Diagram T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 CK CK Command Address DQS DQS DQ BL8 Dout b Dou...

Page 72: ...CARE Power Down Entery DQS DQS DQ BL8 DQ BC4 Start Internal Precharge A10 CKE Note 1 tWR is programmed through MR0 Figure 61 Power Down Entry after Write with Auto Precharge T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4...

Page 73: ...ower Down Mode tPD Command CKE TIME BREAK DON T CARE VALID Figure 63 Precharge Power Down Fast Exit Mode Entry and Exit T0 T1 T2 Ta0 Tb0 Tb1 Tc0 CK CK NOP NOP tIS Ta1 NOP NOP NOP VALID VALID tIH tIS t...

Page 74: ...S tCPDED Command Address VALID NOP T3 VALID CKE CK TIME BREAK DON T CARE VALID VALID Figure 65 Refresh Command to Power Down Entry T0 T1 T2 Ta0 CK ACTIVE NOP Ta1 NOP VALID VALID tPD tACTPDEN tIS tCPDE...

Page 75: ...N tIS tCPDED Command Address VALID NOP T3 VALID CKE CK TIME BREAK DON T CARE VALID VALID Figure 67 Precharge Precharge all Command to Power Down Entry T0 T1 Ta0 Tb0 MRS NOP Tb1 NOP VALID VALID tPD tMR...

Page 76: ...E intensive operations for example repeated PD Exit Refresh PD Entry sequences the number of clock cycles between PD Exit and PD Entry may be insufficient to keep the DLL updated Therefore the followi...

Page 77: ...the Refresh command is satisfied This means CKE cannot be registered low twice within a tRFC min window A detailed example of Case 3 is shown in Figure 71 T0 T1 T2 Ta1 CK CK REF NOP Tb0 NOP NOP NOP t...

Page 78: ...CK for all speed bins assuming the maximum sensitivities specified in the Output Driver Voltage and Temperature Sensitivity and ODT Voltage and Temperature Sensitivity tables The appropriate interval...

Page 79: ...rmination must be disabled via the ODT signal or MRS during the calibration procedure 3 All devices connected to the DQ bus should be high impedance during the calibration procedure Figure 72 ZQ Calib...

Page 80: ...tation of the DRAM ODT feature is shown in Figure 73 VDDQ 2 Swtich ODT RTT To other circuitry like RCV DQ DQS DM Figure 73 Functional Representation of ODT The switch is enabled by the internal ODT co...

Page 81: ...y Symbol Parameter DDR3L 1333 1600 1866 2133 Unit ODTLon ODT turn on Latency WL 2 CWL AL 2 nCK ODTLoff ODT turn off Latency WL 2 CWL AL 2 8 19 2 2 Timing Parameters In synchronous ODT mode the followi...

Page 82: ...CARE Figure 74 Synchronous ODT Timing AL 3 CWL 5 ODTLon AL CWL 2 6 ODTLoff AL CWL 2 6 T0 T1 T2 T4 CK CK T5 T3 ODT T6 T7 tAONmin T8 T9 T10 T12 T13 T14 T15 T11 tAONmax Rtt_Nom tAOFmin tAOFmax CKE DRAM_...

Page 83: ...timing may apply If DRAM stops driving late i e tHZ is late then DRAM complies with tAONmax timing Note that ODT may be disabled earlier before the Read and enabled later after the Read than shown in...

Page 84: ...write command WR WRA WRS4 WRS8 WRAS4 WRAS8 is registered and if Dynamic ODT is enabled the termination is controlled as follows A latency ODTLcnw after the write command termination strength Rtt_WR is...

Page 85: ...e after Write BL 4 ODTH4 Registering Write with ODT high ODT registered low ODTH4 4 tCK avg Minimum ODT high time after Write BL 8 ODTH8 Registering Write with ODT high ODT registered low ODTH4 6 tCK...

Page 86: ...ODTLcwn4 tADCmax tADCmin tAOFmax tAOFmin WL WRS4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP RTT DQ DQS DQS Rtt_WR Rtt_Nom TRANSITIONING DON T CARE NOTES Example for BC4 via MRS or OTF AL 0 CW...

Page 87: ...egistered low at T5 would also be legal Figure 78 Dynamic ODT Behavior without write command AL 0 CWL 5 T0 T1 T2 T4 CK CK DON T CARE T5 T3 ODT T6 T7 T8 T9 T10 T11 NOP TRANSITIONING tAOFmin Address Rtt...

Page 88: ...tered low at T5 would also be legal Figure 80 Dynamic ODT Behavior with ODT pin being asserted together with write command for duration of 6 clock cycles example for BC4 via MRS or OTF AL 0 CWL 5 T0 T...

Page 89: ...resistance is fully on tAONPDmin and tAONPDmax are measured from ODT being sampled high Minimum RTT turn off time tAOFPDmin is the point in time when the devices termination circuit starts to turn off...

Page 90: ...min starts with the clock cycle where CKE is first registered low The transition period begins with the starting point of tANPD and terminates at the end point of tCPDED min as shown in Figure 83 If t...

Page 91: ...Dmin RTT tAOFPDmax NOP NOP NOP NOP NOP NOP tCPDED tCPDEDmin tANPD ODTLoff PD entry transition period tAOFPDmax ODTLoff tAOFmin ODTLoff tAOFmax PD entry transition period tAOFPDmin CKE RTT Sync or asyn...

Page 92: ...NOP NOP REF NOP RTT RTT tAOFPDmax Last sync ODT RTT Sync or async ODT RTT First async ODT tAOFPDmin ODTLoff tAOFPDmax tAOFPDmin tRFC min ODTLoff tAOFPDmin PD entry transition period tCPDEDmin tANPD OD...

Page 93: ...ertion during the transition period may result in an RTT change as early as the smaller of tAOFPDmin and ODTLoff tCK avg tAOFmin and as late as the larger of tAOFPDmax and ODTLoff tCK avg tAOFmax See...

Page 94: ...ansition periods for PD exit and PD entry may overlap In this case the response of the DDR3L SDRAMs RTT to a change in ODT state at the input may be synchronous OR asynchronous from the start of the P...

Page 95: ...BC4 on the Fly WRS4 H H L H L L BA RFU L L CA 5 Write BL8 on the Fly WRS8 H H L H L L BA RFU H L CA 5 Write with Auto Precharge Fixed BL8 or BC4 WRA H H L H L L BA RFU V H CA 5 Write with Auto Precha...

Page 96: ...described in this table The ODT function is not available during Self Refresh 8 Self Refresh Exit is asynchronous 9 VREF Both VREFDQ and VREFCA must be maintained during Self Refresh operation VREFDQ...

Page 97: ...on of CKE H L or CKE L H the CKE level must be maintained until 1nCK prior to tCKEmin being satisfied at which time CKE may transition again 7 DESELECT and NOP are defined in the Command Truth Table 8...

Page 98: ...From any state RESET ZQCL MRS SRE SRX REF PDE PDX ACT ZQCL ZQCS PDX PDE Write Read Read A Write A Write A Read A PRE PREA PRE PREA PRE PREA Write A Read Write Write Read CKE_L CKE_L CKE_ L Automatic s...

Page 99: ...PER 40 85 C 1 3 40 105 C 1 3 4 Notes 1 Operating Temperature TOPER is the case surface temperature on the center top side of the DRAM For measurement conditions please refer to the JEDEC document JESD...

Page 100: ...ad presented by a production tester System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment Manufacturers correlate to their productio...

Page 101: ...a simplified symbol for VIL CA AC160 VIL CA AC135 and VIL CA AC125 VIL CA AC160 value is used when VREF 0 16V is referenced VIL CA AC135 value is used when VREF 0 135V is referenced and VIL CA AC125...

Page 102: ...C tolerance and VREF AC noise limits The voltage levels for setup and hold time measurements VIH AC VIH DC VIL AC and VIL DC are dependent on VREF VREF shall be understood as VREF DC as defined in Fig...

Page 103: ...K CK use VIH CA AC VIL CA AC of ADD CMD and VREFCA for DQSL DQSL DQSU DQSU use VIH DQ AC VIL DQ AC of DQs and VREFDQ if a reduced AC high or AC low level is used for a signal group then the reduced le...

Page 104: ...oximately the AC levels VIH DQ AC VIL DQ AC for DQ signals in every half cycle preceding and following a valid transition Note that the applicable ac levels for ADD CMD and DQ s might be different per...

Page 105: ...For single ended components of differential signals the requirement to reach VSELmax VSEHmin has no bearing on timing but adds a restriction on the common mode characteristics of these signals 10 6 5...

Page 106: ...signals See section 10 16 5 Data Setup Hold and Slew Rate Derating on page 157 for single ended slew rate definitions for data signals 10 6 7 Slew Rate Definitions for Differential Input Signals Inpu...

Page 107: ...d of 25 to VTT VDDQ 2 at each of the differential outputs 10 7 1 Output Slew Rate Definition and Requirements The slew rate definition depends if the signal is single ended or differential For the rel...

Page 108: ...e 27 and Figure 94 Table 27 Single ended Output Slew Rate Definition Description Measured Defined by from to Single ended output slew rate for rising edge VOL AC VOH AC VOH AC VOL AC TRse Single ended...

Page 109: ...28 Differential Output Slew Rate Definition Description Measured Defined by from to Differential output slew rate for rising edge VOL DIFF AC VOH DIFF AC VOH DIFF AC VOL DIFF AC TRdiff Differential o...

Page 110: ...ted via MR1 settings RON34 RZQ 7 nominal 34 3 10 with nominal RZQ 240 RON40 RZQ 6 nominal 40 0 10 with nominal RZQ 240 The individual pull up and pull down resistors RONPu and RONPd are defined as fol...

Page 111: ...Q 6 1 2 3 VOMDC 0 5 VDDQ 0 9 1 0 1 15 RZQ 6 1 2 3 VOHDC 0 8 VDDQ 0 6 1 0 1 15 RZQ 6 1 2 3 Mismatch between pull up and pull down MMPuPd VOMDC 0 5 VDDQ 10 10 1 2 4 Notes 1 The tolerance limits are spec...

Page 112: ...Driver Sensitivity Definition MIN MAX UNIT RONPU VOHDC 0 6 dRONdTH T dRONdVH V 1 1 dRONdTH T dRONdVH V RZQ 7 RON VOMDC 0 9 dRONdTM T dRONdVM V 1 1 dRONdTM T dRONdVM V RZQ 7 RONPD VOLDC 0 6 dRONdTL T d...

Page 113: ...d DQS DQS pins A functional representation of the on die termination is shown in Figure 97 The individual pull up and pull down resistors RTTPu and RTTPd are defined as follows RTTPu Out Out DDQ I V V...

Page 114: ...ensitivity 3 The tolerance limits are specified under the condition that VDDQ VDD and that VSSQ VSS 4 Measurement definition for RTT Apply VIH AC to pin under test and measure current I VIH AC then ap...

Page 115: ...ISFPUPD 1 2 3 4 5 RTT60PU120 VOMDC 0 5 VDDQ 0 9 1 0 1 15 RZQ TISFPUPD 1 2 3 4 5 RTT40PU80 VOHDC 0 8 VDDQ 0 6 1 0 1 15 RZQ TISFPUPD 1 2 3 4 5 RTT30PU60 RTT20PU40 Notes 1 TISFPUPD Termination Impedance...

Page 116: ...DTLon Extrapolated point at VSSQ Figure 99 tAONPD Rising edge of CK CK with ODT being first registered high Extrapolated point at VSSQ Figure 100 tAOF Rising edge of CK CK defined by the end point of...

Page 117: ...at VSSQ DQ DM DQS DQS Begin point Rising edge of CK CK defined by the end point of ODTL on VTT VSSQ Figure 99 Definition of tAON CK CK tAONPD VSSQ VSW2 VSW1 TSW1 TSW2 End point Extrapolated point at V...

Page 118: ...Q DM DQS DQS Begin point Rising edge of CK CK defined by the end point of ODTLoff VTT VSSQ VRtt_Nom Figure 101 Definition of tAOF CK CK tAOFPD VSW2 VSW1 TSW1 TSW2 End point Extrapolated point at VRtt_...

Page 119: ...polated point at VRtt_Nom DQ DM DQS DQS Begin point Rising edge of CK CK defined by the end point of ODTLcnw VRtt_Nom tADC TSW1 TSW2 End point Extrapolated point at VRtt_WR Begin point Rising edge of...

Page 120: ...DQS CDIO 0 5 0 3 0 5 0 3 0 5 0 3 0 5 0 3 pF 2 3 11 Input output capacitance of ZQ signal CZQ 3 3 3 3 pF 2 3 12 Notes 1 Although the DM signals have different functions the loading matches DQ and DQS...

Page 121: ...and peak amplitude undershoot voltage is not to exceed absolute maximum DC ratings 10 12 2 AC Overshoot Undershoot Specification for Clock Data Strobe and Mask Pins Applies to CK CK DQ DQS DQS DM PARA...

Page 122: ...e PCB For IDD and IDDQ measurements the following definitions apply 0 and LOW is defined as VIN VILAC max 1 and HIGH is defined as VIN VIHAC min MID LEVEL is defined as inputs are VREF VDD 2 Timings u...

Page 123: ...load condition may be different from above Figure 105 Measurement Setup and Test Load for IDD and IDDQ optional Measurements Application specific memory channel environment Channel IO Power simulation...

Page 124: ...d in Mode Registers 2 ODT Signal toggling according to Table 43 Pattern Details see Table 43 IDDQ2NT Precharge Standby ODT IDDQ Current Same definition like for IDD2NT however measuring IDDQ current i...

Page 125: ...ure Range SRT Normal 5 CKE Low External clock Off CK and CK LOW CL see Table 38 BL 8 1 AL 0 CS Command Address Bank Address Data IO MID LEVEL DM stable at 0 Bank Activity Self Refresh operation Output...

Page 126: ...1 1 0 0 0 0 0 F 0 1 nRC 1 2 D D 1 0 0 0 0 0 0 0 0 F 0 1 nRC 3 4 D D 1 1 1 1 0 0 0 0 0 F 0 Repeat pattern nRC 1 4 until nRC nRAS 1 truncate if necessary 1 nRC nRAS PRE 0 0 1 0 0 0 0 0 0 F 0 Repeat patt...

Page 127: ...1 1 1 1 0 0 0 0 0 F 0 Repeat pattern nRC 1 4 until nRC nRCD 1 truncate if necessary 1 nRC nRCD RD 0 1 0 1 0 0 0 0 0 F 0 00110011 Repeat pattern nRC 1 4 until nRC nRAS 1 truncate if necessary 1 nRC nR...

Page 128: ...Sub Loop 0 use BA 2 0 7 instead Notes 1 DM must be driven LOW all the time DQS DQS are MID LEVEL 2 DQ signals are MID LEVEL Table 43 IDD2NT and IDDQ2NT Measurement Loop Pattern1 CK CK CKE Sub Loop Cyc...

Page 129: ...Commands otherwise MID LEVEL 2 Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Table 45 IDD4W Measurement Loop Pattern1 CK CK CKE Sub Loop Cyc...

Page 130: ...D 1 0 0 0 0 0 0 0 0 0 0 3 4 D D 1 1 1 1 0 0 0 0 0 F 0 5 8 Repeat cycles 1 4 but BA 2 0 1 9 12 Repeat cycles 1 4 but BA 2 0 2 13 16 Repeat cycles 1 4 but BA 2 0 3 17 20 Repeat cycles 1 4 but BA 2 0 4 2...

Page 131: ...9 nFAW 4 nRRD D 1 0 0 0 0 7 0 0 0 F 0 Assert and repeat above D Command until 2 nFAW 1 if necessary 10 2 nFAW 0 ACT 0 0 1 1 0 0 0 0 0 F 0 2 nFAW 1 RDA 0 1 0 1 0 0 0 1 0 F 0 00110011 2 nFAW 2 D 1 0 0 0...

Page 132: ...W Operating Burst Write Current 185 210 235 260 mA IDD5B Burst Refresh Current 175 180 190 195 mA IDD6 3 Normal Temperature Self Refresh Current 15 15 15 15 mA IDD6ET 4 Extended Temperature Self Refre...

Page 133: ...consecutive rising edge tCK abs is not subject to production test Definition for tCH avg and tCL avg tCH avg is defined as the average high pulse width as calculated across any consecutive 200 high pu...

Page 134: ...Maximum operating frequency using maximum allowed settings for Sup_CL and Sup_CWL fCKMAX 667 MHz Internal read command to first data tAA 13 5 13 125 10 20 nS ACT to internal read or write delay time...

Page 135: ...CWL 6 7 8 tCK AVG Reserved nS 5 CL 6 CWL 5 tCK AVG 2 5 3 3 nS 1 2 3 4 7 CWL 6 7 8 tCK AVG Reserved nS 5 CL 7 CWL 5 tCK AVG Reserved nS 5 CWL 6 tCK AVG 1 875 2 5 nS 1 2 3 4 7 Optional 10 nS 5 CWL 7 8...

Page 136: ...S 5 CL 6 CWL 5 tCK AVG 2 5 3 3 nS 1 2 3 4 8 CWL 6 7 8 9 tCK AVG Reserved nS 5 CL 7 CWL 5 Reserved nS 5 CWL 6 1 875 2 5 nS 1 2 3 4 8 Optional 11 nS CWL 7 8 9 Reserved nS 5 CL 8 CWL 5 tCK AVG Reserved n...

Page 137: ...S 1 2 3 4 9 CWL 6 7 8 9 10 tCK AVG Reserved nS 5 CL 7 CWL 5 tCK AVG Reserved nS 5 CWL 6 tCK AVG 1 875 2 5 nS 1 2 3 4 9 CWL 7 8 9 10 tCK AVG Reserved nS 5 CL 8 CWL 5 tCK AVG Reserved nS 5 CWL 6 tCK AVG...

Page 138: ...not subject to Production Tests but verified by Design Characterization 8 Any DDR3L 1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject...

Page 139: ...Clock Period Jitter during DLL locking period 40 40 50 50 pS tJIT cc Cycle to Cycle Period Jitter 100 120 pS tJIT cc lck Cycle to Cycle Period Jitter during DLL locking period 80 100 pS tJIT duty Cloc...

Page 140: ...differential WRITE Preamble 0 9 0 9 tCK avg 46 tWPST DQS DQS differential WRITE Postamble 0 3 0 3 tCK avg 46 tDQSCK DQS DQS rising edge output access time from rising CK CK 180 180 195 195 pS 17 23 tL...

Page 141: ...F 1 V nS 195 200 pS 9 41 42 tIPW Control address and control input pulse width for each input 470 535 pS 10 Calibration Timing tZQinit Power up and RESET calibration time max 512nCK 640nS max 512nCK 6...

Page 142: ...CK 19 tWRPDEN Timing of WR command to Power Down entry BC4MRS Min WL 2 roundup tWR min tCK avg Max nCK 20 tWRAPDEN Timing of WRA command to Power Down entry BC4MRS Min WL 2 WR 1 Max nCK 19 tREFPDEN Ti...

Page 143: ...er during DLL locking period 60 60 70 70 pS tJIT cc Cycle to Cycle Period Jitter 140 160 pS tJIT cc lck Cycle to Cycle Period Jitter during DLL locking period 120 140 pS tJIT duty Clock Duty Cycle Jit...

Page 144: ...erential WRITE Preamble 0 9 0 9 tCK avg 46 tWPST DQS DQS differential WRITE Postamble 0 3 0 3 tCK avg 46 tDQSCK DQS DQS rising edge output access time from rising CK CK 225 225 255 255 pS 17 23 tLZ DQ...

Page 145: ...41 VREF 1 V nS 220 240 pS 9 41 42 tIPW Control address and control input pulse width for each input 560 620 pS 10 Calibration Timing tZQinit Power up and RESET calibration time max 512nCK 640nS max 5...

Page 146: ...x nCK 19 tWRPDEN Timing of WR command to Power Down entry BC4MRS Min WL 2 roundup tWR min tCK avg Max nCK 20 tWRAPDEN Timing of WRA command to Power Down entry BC4MRS Min WL 2 WR 1 Max nCK 19 tREFPDEN...

Page 147: ...device will support tnRP RU tRP tCK avg 9 as long as the input clock jitter specifications are met i e Precharge command at Tm and Active command at Tm 9 is valid even if Tm 9 Tm is less than 13 5nS d...

Page 148: ...RPDEN it is necessary to round up tWR min tCK avg to the next integer value 21 The maximum read preamble is bound by tLZ DQS min on the left side and tDQSCK max on the right side See Figure 24 READ Ti...

Page 149: ...tionship between the average timing tCK avg and the respective absolute instantaneous timing tCK abs holds all times 38 tCH abs is the absolute instantaneous clock high pulse width as measured from on...

Page 150: ...ate line anywhere between shaded DC to VREF DC region the slew rate of a tangent line to the actual signal from the DC level to VREF DC level is used for derating value see Figure 110 For a valid tran...

Page 151: ...16 4 24 14 32 30 0 5 20 30 20 30 20 30 12 22 4 14 4 6 12 4 20 20 0 4 40 45 40 45 40 45 32 37 24 29 16 21 8 11 0 5 Table 50 Derating values DDR3L 1333 1600 tIS tIH AC DC based Alternate AC135 Threshold...

Page 152: ...7 21 35 31 43 47 0 8 6 8 6 8 6 8 14 1 22 9 30 17 38 27 46 43 0 7 10 13 10 13 10 13 18 5 26 3 34 11 42 21 50 37 0 6 16 20 16 20 16 20 24 12 32 4 40 4 48 14 56 30 0 5 15 30 15 30 15 30 23 22 31 14 39 6...

Page 153: ...to AC region nominal slew rate VREF to AC region tVAC TF TR Setup Slew Rate Falling Signal VREF DC VIL AC max TF Setup Slew Rate Rising Signal VIH AC min VREF DC TR tDS tDH tDS tDH Note Clock and Stro...

Page 154: ...gion nominal slew rate DC to VREF region TF TR tDS tDH tDS tDH Note Clock and Strobe are drawn on a different time scale Hold Slew Rate Rising Signal VREF DC VIL DC max TR Hold Slew Rate Falling Signa...

Page 155: ...nal line nominal line tVAC tVAC Setup Slew Rate Rising Signal tangent line VIH AC min VREF DC TR Setup Slew Rate Falling Signal tangent line VREF DC VIL AC max TF tIS tIH tIS tIH tDS tDH tDS tDH Note...

Page 156: ...Signal tangent line VREF DC VIL DC max TR DC to VREF region tangent line nominal line Hold Slew Rate Falling Signal tangent line VIH DC min VREF DC TF tIS tIH tIS tIH tDS tDH tDS tDH Note Clock and S...

Page 157: ...rate between the last crossing of VIH DC min and the first crossing of VREF DC see Figure 108 If the actual signal is always later than the nominal slew rate line between shaded DC level to VREF DC r...

Page 158: ...S DQS Differential Slew Rate 8 0 V nS 7 0 V nS 6 0 V nS 5 0 V nS 4 0 V nS 3 0 V nS 2 0 V nS 1 8 V nS 1 6 V nS 1 4 V nS 1 2 V nS 1 0 V nS tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH...

Page 159: ...Conditions DDR3 1 5V operation Symbol Parameter Condition Min Typ Max Unit Notes VDD Supply Voltage 1 425 1 5 1 575 V 1 2 3 VDDQ Supply Voltage for Output 1 425 1 5 1 575 V 1 2 3 Notes 1 If minimum l...

Page 160: ...rmed tZQinit must be satisfied after the 1 35V operating voltages are stable and prior to any READ command After the DDR3L DRAM is powered up and initialized the power supply can be altered between th...

Page 161: ...OW CONDITION THE WINDOW SIDE ENCAPSULANT T eee C A C B M ddd M 4X BALL LAND BALL OPENING Note 1 Ball land 0 5mm Ball opening 0 4mm PCB Ball land suggested 0 4mm 1 4 5 6 A SYMBOL DIMENSION MIN NOM MAX...

Page 162: ...W632GU6NB Publication Release Date Aug 20 2018 Revision A01 162 13 REVISION HISTORY VERSION DATE PAGE DESCRIPTION A01 Aug 20 2018 All Initial formal datasheet...

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