W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 133 -
10.14 Clock Specification
The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the
min/max values may result in malfunction of the DDR3L SDRAM device.
Definition for tCK(avg)
t
CK(avg)
is calculated as the average clock period across any consecutive 200 cycle window, where
each clock period is calculated from rising edge to rising edge.
t
CK
(
avg
) =
N
j
j
tCK
1
/
N
where
N
= 200
Definition for tCK(abs)
t
CK(abs)
is defined as the absolute clock period, as measured from one rising edge to the next
consecutive rising edge. t
CK(abs)
is not subject to production test.
Definition for tCH(avg) and tCL(avg)
t
CH(avg)
is defined as the average high pulse width, as calculated across any consecutive 200 high
pulses.
t
CH
(
avg
) =
N
j
j
tCH
1
/ (
N
×
t
CK
(
avg
))
where
N
= 200
t
CL(avg)
is defined as the average low pulse width, as calculated across any consecutive 200 low
pulses.
t
CL
(
avg
) =
N
j
j
tCL
1
/ (
N
×
t
CK
(
avg
))
where
N
= 200
Definition for tJIT(per) and tJIT(per,lck)
t
JIT(per)
is defined as the largest deviation of any signal t
CK
from t
CK(avg)
.
t
JIT(per)
= Min/max of {t
CK
i - t
CK(avg)
where i = 1 to 200}.
t
JIT(per)
defines the single period jitter when the DLL is already locked.
t
JIT(per,lck)
uses the same definition for single period jitter, during the DLL locking period only.
t
JIT(per)
and t
JIT(per,lck)
are not subject to production test.
