W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 138 -
10.15.5 Speed Bin General Notes
The absolute specification for all speed bins is T
OPER
and V
DD
= V
DDQ
= 1.283V to 1.45V. In addition
the following general notes apply.
1. Max. limits are exclusive. E.g. if t
CK(AVG).MAX
value is 2.5 nS, t
CK(AVG)
needs to be < 2.5 nS.
2. The CL setting and CWL setting result in t
CK(AVG).MIN
and t
CK(AVG).MAX
requirements. When making
a selection of t
CK(AVG)
, both need to be fulfilled: Requirements from CL setting as well as
requirements from CWL setting.
3. t
CK(AVG).MIN
limits: Since CAS Latency is not purely analog - data and strobe output are
synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An
application should use the next smaller standard t
CK(AVG)
value (3.0, 2.5, 1.875, 1.5, 1.25, 1.07 or
0.938 nS) when calculating CL [nCK] = t
AA
[nS] / t
CK(AVG)
[nS
], rounding up to the next ‘Supported
CL’.
4. t
CK(AVG).MAX
limits: Calculate t
CK(AVG)
= t
AA.MAX
/ CL SELECTED and round the resulting t
CK(AVG)
down to the next valid speed bin (i.e. 3.3 nS or 2.5 nS or 1.875 nS or 1.5 nS or 1.25 nS or 1.07 nS).
This result is t
CK(AVG).MAX
corresponding to CL SELECTED.
5.
‘Reserved’ settings are not allowed. User must program a different value.
6. Any DDR3L-1333 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
7. Any DDR3L-1600 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
8. Any DDR3L-1866 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
9. Any DDR3L-2133 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
10. For devices supporting optional down binning to CL=7 and CL=9, t
AA
/t
RCD
/t
RP
min must be 13.125
nS. SPD settings must be programmed to match. For example, DDR3L-1333 (9-9-9) devices
supporting down binning to DDR3L-1066 (7-7-7) should program 13.125 nS in SPD bytes for
t
AA
min (Byte 16), t
RCD
min (Byte 18), and t
RP
min (Byte 20). DDR3L-1600 (11-11-11) devices
supporting down binning to DDR3L-1333 (9-9-9) or DDR3L-1066 (7-7-7) should program 13.125
nS in SPD bytes for t
AA
min (Byte16), t
RCD
min (Byte 18), and t
RP
min (Byte 20). Once t
RP
(Byte 20)
is programmed to 13.125 nS, t
RC
min (Byte 21, 23) also should be programmed accordingly. For
example, 49.125nS (t
RAS
min + t
RP
min = 36 nS + 13.125 nS) for DDR3L-1333 (9-9-9) and 48.125
nS (t
RAS
min + t
RP
min = 35 nS + 13.125 nS) for DDR3L-1600 (11-11-11).
11. For devices supporting optional down binning to CL=11, CL=9 and CL=7, t
AA
/t
RCD
/t
RP
min must be
13.125 nS. SPD settings must be programmed to match. For example, DDR3L-1866 (13-13-13)
devices supporting down binning to DDR3L-1600 (11-11-11) or DDR3L-1333 (9-9-9) or DDR3L-
1066 (7-7-7) should program 13.125 nS in SPD bytes for t
AA
min (Byte 16), t
RCD
min (Byte 18), and
t
RP
min (Byte 20). Once t
RP
(Byte 20) is programmed to 13.125 nS, t
RC
min (Byte 21, 23) also
should be programmed accordingly. For example, 47.125nS (t
RAS
min + t
RP
min = 34 nS + 13.125
nS).
