W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 150 -
10.16.4 Address / Command Setup, Hold and Derating
For all input signals the total t
IS
(setup time) and t
IH
(hold time) required is calculated by adding the
datasheet t
IS(base)
and t
IH(base)
value (see Table 48
) to the Δt
IS
and Δt
IH
derating value (see Table 49
to Table 51) respectively. Example: t
IS
(total setup time) = t
IS(base)
+ Δt
IS.
Setup (t
IS
) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
V
REF(DC)
and the first crossing of V
IH(AC)
min. Setup (t
IS
) nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of V
REF(DC)
and the first crossing of V
IL(AC)
max. If
the actual signal
is always earlier than the nominal slew rate line between shaded ‘V
REF(DC)
to AC
region’, use nominal slew rate for derating value (see Figure 107). If the actual signal is later than the
nominal slew rate line
anywhere between shaded ‘V
REF(DC)
to AC region’, the slew rate of a tangent
line to the actual signal from the AC level to V
REF(DC)
level is used for derating value (see Figure 109).
Hold (t
IH
) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
V
IL(DC)
max and the first crossing of V
REF(DC)
. Hold (t
IH
) nominal slew rate for a falling signal is defined
as the slew rate between the last crossing of V
IH(DC)
min and the first crossing of V
REF(DC)
. If the actual
signal
is always later than the nominal slew rate line between shaded ‘DC to V
REF(DC)
region’, use
nominal slew rate for derating value (see Figure 108). If the actual signal is earlier than the nominal
slew rate line anywhere
between shaded ‘DC to V
REF(DC)
region’, the slew rate of a tangent line to the
actual signal from the DC level to V
REF(DC)
level is used for derating value (see Figure 110).
For a valid transition the input signal has to remain above/below V
IH/IL(AC)
for some time t
VAC
(see
Table 52).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not
have reached V
IH/IL(AC)
at the time of the rising clock transition, a valid input signal is still required to
complete the transition and reach V
IH/IL(AC)
.
For slew rates in between the values listed in the tables, the derating values may obtained by linear
interpolation.
These values are typically not subject to production test. They are verified by design and
characterization.
Table 48
– ADD/CMD Setup and Hold Base-Values for 1V/nS
Symbol
Reference
DDR3L-1333 DDR3L-1600 DDR3L-1866 DDR3L-2133 Unit Note
t
IS(base)
AC160
V
IH/L(AC)
: SR=1 V/nS
80
60
-
-
pS
1
t
IS(base) AC135
V
IH/L(AC)
: SR=1 V/nS
205
185
65
60
pS
1, 2
t
IS(base) AC125
V
IH/L(AC)
: SR=1 V/nS
-
-
150
135
pS
1, 3
t
IH(base) DC90
V
IH/L(DC)
: SR=1 V/nS
150
130
110
105
pS
1
Notes:
1. (AC/DC referenced for 1V/nS Address/Command slew rate and 2 V/nS differential CK-CK# slew rate)
2. The t
IS(base) AC135
specifications are adjusted from the t
IS(base) AC160
specification by adding an additional 100pS for
DDR3L-1333/1600 of derating to accommodate for the lower alternate threshold of 135 mV and another 25 pS to account
for the earlier reference point [(160 mV - 135 mV) / 1 V/nS].
3. The t
IS(base) AC125
specifications are adjusted from the t
IS(base) AC135
specification by adding an additional 75 pS for
DDR3L-1866 or 65pS for DDR3L-2133 of derating to accommodate for the lower alternate threshold of 125 mV and another
10 pS to account for the earlier reference point [(135 mV - 125 mV) / 1 V/nS].
