Data Tab:
User selects a test pattern that will be encapsulated in the Ethernet frame payload (for framed mode).
Depending on the test layer, different test pattern options are available.
Layer 1 Framed Test Patterns
CRPAT:
Compliant Random Pattern provides broad spectral content and minimal peaking for the measurement
of jitter at component or system level.
CJTPAT:
Compliant Jitter Test Pattern is a Jitter Tolerance Pattern that stresses a receiver by exposing it to
extreme phase jumps thereby stressing the clock data recovery (CDR) circuitry. The pattern alternates between
repeating low transition density patterns and repeating high transition density patterns.
CSPAT:
Compliant Supply Noise Pattern. Represents worst case power supply noise.
BERT Setup - Data selection (Layer 1 Framed)
BERT Setup - Data selection - (Layer 1 Unframed)
Layer 1 Unframed Test Patterns
HFPAT (High Frequency Pattern):
This test pattern is to test random jitter (RJ) at a BER of 10-12, and also to
test the asymmetry of transition times. This high frequency test pattern generates a one, or light on, for a
duration of 1 bit time, followed by a zero, or light off, for a duration of 1 bit time. This pattern can be generated
by the repeated transmission of the D21.5 code-group. Disparity rules are followed.
LFPAT (Low Frequency Pattern):
The intent of this test pattern is to test low frequency RJ and also to test
PLL tracking error. This low frequency test pattern generates a one, or light on, for a duration of 5 bit times,
followed by a zero, or light off, for a duration of 5 bit times. This pattern can be generated by the repeated
transmission of the K28.7 code-group. Disparity rules are followed.
MFPAT (Mixed Frequency Pattern):
The intent of this test pattern is to test the combination of RJ and
deterministic jitter (DJ). This mixed frequency test pattern generates a one, or light on, for a duration of 5 bit
times, followed by a zero, or light off, for a duration of 1 bit times, followed by a one for 1 bit time followed by a
zero for 1 bit time followed by a one for 2 bit times followed by a zero for 5 bit times followed by a one for 1 bit
time followed by a zero for 1 bit time followed by a one for 1 bit time followed by a zero for 2 bit times. This
pattern can be generated by the repeated transmission of the K28.5 code-group. Disparity rules are followed.
RXT-6400_Module_Manual
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