Themis RES-XR4-1U, Installation Manual

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RES-XR4-1U Installation Manual Version 1.5
3-8
Themis Computer
3.3.3.6 Limit CPUID Maximum
This feature allows the user to set the maximum CPU ID value. Enable this function
to boot the legacy operating systems that cannot support processors with extended-
CPUID functions. The options are Enabled and
Disabled (for the Windows OS).
3.3.3.7 Execute-Disable Bit Capability (Available when supported by
the OS and the CPU)
Set to Enabled to enable the Execute Disable Bit which will allow the processor to
delegate areas in the system memory where an application code can execute and
where it cannot, thus preventing a worm or a virus from flooding illegal codes to
overwhelm the processor or damage the system during an attack. The default is
Enabled (default). (Refer to Intel and Microsoft Web Sites for more information.)
3.3.3.8 Intel
®
AES-NI
Select Enable to use the Intel Advanced Encryption Standard (AES) New Instruc-
tions (NI) to ensure data security. The options are
Enabled (default) and Disabled .
3.3.3.9 Hardware Prefetcher (Available when supported by the CPU)
If set to Enabled, the hardware pre fetcher will pre fetch streams of data and instruc-
tions from the main memory to the L2 cache in the forward or backward manner to
improve CPU performance. The options are Disabled and
Enabled (default).
3.3.3.10 Adjacent Cache Line Prefetcher (Available when supported by
the CPU)
If this feature is set to Disabled, The CPU prefetches the cache line for 64 bytes. If
this feature is set to Enabled the CPU fetches both cache lines for 128 bytes as com-
prised. The options are Disabled and
Enabled.
3.3.3.11 DCU Streamer Prefetcher (Available when supported by the
CPU)
Select Enabled to support Data Cache Unit (DCU) prefetch of L1 data to speed up
data accessing and processing in the DCU to enhance CPU performance. The
options are Disabled and
Enabled .
3.3.3.12 DCU IP Prefetcher
Select Enabled for DCU (Data Cache Unit) IP Prefetcher support, which will